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Levent Aksoy
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2020 – today
- 2024
- [c41]Levent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini:
Multiplierless Design of High-Speed Very Large Constant Multiplications. ASPDAC 2024: 957-962 - [c40]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. DATE 2024: 1-6 - [c39]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. LATS 2024: 1-6 - [i11]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. CoRR abs/2401.07142 (2024) - [i10]Felipe Almeida, Levent Aksoy, Samuel Pagliarini:
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. CoRR abs/2409.16959 (2024) - 2023
- [j15]Levent Aksoy
, Quang-Linh Nguyen, Felipe Almeida
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 812-825 (2023) - [c38]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini:
Resynthesis-based Attacks Against Logic Locking. ISQED 2023: 1-8 - [i9]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini:
Resynthesis-based Attacks Against Logic Locking. CoRR abs/2301.04400 (2023) - [i8]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
Hybrid Protection of Digital FIR Filters. CoRR abs/2301.11115 (2023) - [i7]Levent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini:
Multiplierless Design of High-Speed Very Large Constant Multiplications. CoRR abs/2309.05550 (2023) - [i6]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. CoRR abs/2311.05982 (2023) - 2022
- [j14]Levent Aksoy
Multiplierless Design of Very Large Constant Multiplications in Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4503-4507 (2022) - [j13]Nihat Akkan
Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches. IEEE Trans. Emerg. Top. Comput. 10(1): 351-360 (2022) - [c37]Levent Aksoy, Alexander Hepp, Johanna Baehr
Hardware Obfuscation of Digital FIR Filters. DDECS 2022: 68-73 - [i5]Levent Aksoy, Alexander Hepp, Johanna Baehr, Samuel Pagliarini:
Hardware Obfuscation of Digital FIR Filters. CoRR abs/2202.10022 (2022) - [i4]Levent Aksoy, Debapriya Basu Roy, Malik Imran, Patrick Karl
Multiplierless Design of Very Large Constant Multiplications in Cryptography. CoRR abs/2205.10591 (2022) - 2021
- [j12]Levent Aksoy
Realization of Logic Functions Using Switching Lattices Under a Delay Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2036-2048 (2021) - [c36]Felipe Almeida, Levent Aksoy
Side-Channel Attacks on Triple Modular Redundancy Schemes. ATS 2021: 79-84 - [c35]Levent Aksoy
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS 2021: 1-7 - [i3]Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini:
Side-Channel Attacks on Triple Modular Redundancy Schemes. CoRR abs/2104.04334 (2021) - [i2]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR abs/2105.06122 (2021) - 2020
- [j11]Levent Aksoy
Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices. IEEE Trans. Computers 69(3): 427-440 (2020) - [c34]Ismail Cevik, Levent Aksoy
CMOS Implementation of Switching Lattices. DATE 2020: 274-277 - [c33]Levent Aksoy
A Novel Method for the Realization of Complex Logic Functions using Switching Lattices. ISCAS 2020: 1-5 - [c32]Levent Aksoy
Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks. ISCAS 2020: 1-5 - [c31]Mohammadreza Esmali Nojehdeh, Levent Aksoy
Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks. ISVLSI 2020: 96-101
2010 – 2019
- 2019
- [c30]Serzat Safaltin
Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling. DATE 2019: 504-509 - [c29]Levent Aksoy
A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices. DATE 2019: 1637-1642 - 2016
- [j10]Levent Aksoy
A novel method for the approximation of multiplierless constant matrix vector multiplication. EURASIP J. Embed. Syst. 2016: 12 (2016) - 2015
- [j9]Levent Aksoy
Exact and Approximate Algorithms for the Filter Design Optimization Problem. IEEE Trans. Signal Process. 63(1): 142-154 (2015) - [c28]Levent Aksoy
A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication. EUC 2015: 98-105 - [c27]Levent Aksoy
Approximation of multiple constant multiplications using minimum look-up tables on FPGA. ISCAS 2015: 2884-2887 - 2014
- [j8]Levent Aksoy
A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst. Signal Process. 33(6): 1689-1719 (2014) - [j7]Levent Aksoy
Multiplierless Design of Folded DSP Blocks. ACM Trans. Design Autom. Electr. Syst. 20(1): 14:1-14:24 (2014) - [c26]Levent Aksoy, Paulo F. Flores
Optimization of design complexity in time-multiplexed constant multiplications. DATE 2014: 1-4 - [c25]Levent Aksoy
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. ICCD 2014: 42-47 - [c24]Levent Aksoy
ECHO: A novel method for the multiplierless design of constant array vector multiplication. ISCAS 2014: 1456-1459 - 2013
- [j6]Levent Aksoy
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 498-511 (2013) - [c23]Levent Aksoy, Eduardo Costa
Exploration of tradeoffs in the design of integer cosine transforms for image compression. ECCTD 2013: 1-4 - [c22]Levent Aksoy
SIREN: a depth-first search algorithm for the filter design optimization problem. ACM Great Lakes Symposium on VLSI 2013: 179-184 - [c21]Levent Aksoy
Towards the least complex time-multiplexed constant multiplication. VLSI-SoC 2013: 328-331 - 2012
- [j5]Levent Aksoy
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. 45(3): 294-306 (2012) - [j4]Levent Aksoy
Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17(1): 3:1-3:27 (2012) - [c20]Levent Aksoy, Eduardo Costa
Design of low-complexity digital finite impulse response filters on FPGAs. DATE 2012: 1197-1202 - [c19]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Multiple tunable constant multiplications: Algorithms and applications. ICCAD 2012: 473-479 - 2011
- [j3]Levent Aksoy
Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocess. Microsystems 35(8): 729-741 (2011) - [c18]Levent Aksoy
Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD 2011: 588-591 - [c17]Levent Aksoy
Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66 - [c16]Levent Aksoy
Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI 2011: 79-84 - [c15]Levent Aksoy
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740 - [c14]Levent Aksoy
Multiplierless Design of Linear DSP Transforms. VLSI-SoC (Selected Papers) 2011: 73-93 - [c13]Levent Aksoy
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153 - 2010
- [j2]Levent Aksoy
Search algorithms for the multiple constant multiplications problem: Exact and approximate. Microprocess. Microsystems 34(5): 151-162 (2010) - [c12]Levent Aksoy
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10 - [c11]Sidinei Ghissoni, Eduardo Costa
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862 - [c10]Diego Jaccottet, Eduardo Costa
Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297 - [i1]Nuno P. Lopes, Levent Aksoy, Vasco Manquinho, José Monteiro:
Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability. CoRR abs/1011.2685 (2010)
2000 – 2009
- 2009
- [c9]Levent Aksoy
Design of low complexity digital FIR filters. SBCCI 2009 - 2008
- [j1]Levent Aksoy
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1013-1026 (2008) - [c8]Levent Aksoy
An approximate algorithm for the multiple constant multiplications problem. SBCCI 2008: 58-63 - [c7]Levent Aksoy
Area optimization algorithms in high-speed digital FIR filter synthesis. SBCCI 2008: 64-69 - 2007
- [c6]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423 - [c5]Levent Aksoy
Minimum number of operations under a general number representation for digital filter synthesis. ECCTD 2007: 252-255 - [c4]Levent Aksoy
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS 2007: 424-429 - 2006
- [c3]Levent Aksoy
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674 - [c2]Levent Aksoy
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. ICECS 2006: 748-751 - 2005
- [c1]Levent Aksoy
An Evolutionary Local Search Algorithm for the Satisfiability Problem. TAINN 2005: 185-193
Coauthor Index
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