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Raffaele De Rose
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2020 – today
- 2023
- [j16]Luigi Fassio
, Longyang Lin
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access 11: 3584-3596 (2023) - [j15]Tatiana Moposita
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access 11: 144084-144094 (2023) - [i3]Massimo Vatalaro, H. Neill, F. Gity, Paolo Magnone, V. Maccaronio, C. Márquez, J. C. Galdon, F. Gamiz, Felice Crupi, P. Hurley, Raffaele De Rose:
Experimental analysis of variability in WS2-based devices for hardware security. CoRR abs/2308.02265 (2023) - 2022
- [j14]Massimo Vatalaro
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. IEEE J. Solid State Circuits 57(8): 2509-2520 (2022) - [c15]Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. ICECS 2022 2022: 1-4 - [i2]Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza:
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR abs/2204.09395 (2022) - [i1]Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR abs/2205.09388 (2022) - 2021
- [j13]Luigi Fassio, Longyang Lin
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits 56(10): 3134-3144 (2021) - [j12]Luigi Fassio, Francesco Settino
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1393-1397 (2021) - [j11]Luigi Fassio, Longyang Lin
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3038-3042 (2021) - [c14]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC 2021: 343-346 - 2020
- [j10]Esteban Garzón
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. 71: 56-69 (2020) - [c13]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j9]Raffaele De Rose
Double-precision Dual Mode Logic carry-save multiplier. Integr. 64: 71-77 (2019) - [c12]Marco Lanuzza
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON 2019: 1-4 - [c11]Esteban Garzón
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS 2019: 123-124 - [c10]Marco Lanuzza
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS 2019: 158-161 - [c9]Esteban Garzón
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019: 85-88 - 2018
- [j8]Felice Crupi
A portable class of 3-transistor current references with low-power sub-0.5 V operation. Int. J. Circuit Theory Appl. 46(4): 779-795 (2018) - [j7]Raffaele De Rose
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1086-1095 (2018) - [c8]Raffaele De Rose, Felice Crupi, Maksym Paliy
Design of a 3T current reference for low-voltage, low-power operation. ICICDT 2018: 13-16 - [c7]Noemi Guerra, Raffaele De Rose, Marco Guevara
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. RTSI 2018: 1-4 - 2017
- [j6]Raffaele De Rose
A physical unclonable function based on a 2-transistor subthreshold voltage divider. Int. J. Circuit Theory Appl. 45(2): 260-273 (2017) - [j5]Marco Lanuzza
Low energy/delay overhead level shifter for wide-range voltage conversion. Int. J. Circuit Theory Appl. 45(11): 1637-1646 (2017) - [j4]Marco Lanuzza
An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 61-65 (2017) - [c6]Raffaele De Rose, Domenico Albano, Felice Crupi, Marco Lanuzza
Design of a sub-1-V nanopower CMOS current reference. ECCTD 2017: 1-4 - [c5]Raffaele De Rose
A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS 2017: 1-4 - [c4]Raffaele De Rose
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. SMACD 2017: 1-4 - 2014
- [j3]Raffaele De Rose
Designing Dynamic Carry Skip Adders: Analysis and Comparison. Circuits Syst. Signal Process. 33(4): 1019-1034 (2014) - [c3]Raffaele De Rose, Carmelo Felicetti, Cinzia Raso, Alberto Michele Felicetti, Salvatore Ammirato:
A Framework for Energy-Efficiency in Smart Home Environments. PRO-VE 2014: 237-244 - 2012
- [j2]Marco Lanuzza
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8): 1679-1689 (2012) - [j1]Raffaele De Rose
A methodology to account for the finger interruptions in solar cell performance. Microelectron. Reliab. 52(9-10): 2500-2503 (2012) - 2010
- [c2]Marco Lanuzza
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459 - [c1]Marco Lanuzza
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189
Coauthor Index
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