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Esteban Garzón
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2020 – today
- 2024
- [j16]Esteban Garzón
, Robert Hanhan
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12: 13923-13943 (2024) - [j15]Zuher Jahshan
ViRAL: Vision Transformer Based Accelerator for ReAL Time Lineage Assignment of Viral Pathogens. IEEE Access 12: 28353-28368 (2024) - [j14]Itay Merlin
DIPER: Detection and Identification of Pathogens Using Edit Distance-Tolerant Resistive CAM. IEEE Trans. Computers 73(10): 2463-2473 (2024) - 2023
- [j13]Esteban Garzón
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11: 16812-16819 (2023) - [j12]Hanan Marinberg, Esteban Garzón
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access 11: 94885-94897 (2023) - [j11]Tatiana Moposita
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access 11: 144084-144094 (2023) - [j10]Esteban Garzón
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 408-421 (2023) - [j9]Tatiana Moposita
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1254-1258 (2023) - [j8]Ariana Musello
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1259-1263 (2023) - [j7]Esteban Garzón
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3867-3871 (2023) - [c11]Esteban Garzón
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS 2023: 1-4 - [c10]Zuher Jahshan
DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification. MICRO 2023: 1453-1465 - 2022
- [j6]Esteban Garzón
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10: 28080-28093 (2022) - [j5]Benjamin Zambrano
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification. IEEE Access 10: 94417-94430 (2022) - [j4]Esteban Garzón
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42(6): 67-75 (2022) - [j3]Benjamin Zambrano
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 749-753 (2022) - [c9]Robert Hanhan
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA 2022: 495-507 - [c8]Esteban Garzón
A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS 2022: 2614-2615 - [c7]Esteban Garzón
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS 2022: 1-4 - [i3]Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza:
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR abs/2204.09395 (2022) - [i2]Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Giuseppe Iannaccone, Marco Lanuzza:
A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion. CoRR abs/2209.00815 (2022) - 2021
- [j2]Esteban Garzón
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1319-1324 (2021) - [i1]Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits:
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR abs/2111.09747 (2021) - 2020
- [j1]Esteban Garzón
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. 71: 56-69 (2020) - [c6]Esteban Garzón
Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [c5]Marco Lanuzza
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON 2019: 1-4 - [c4]Esteban Garzón
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS 2019: 123-124 - [c3]Esteban Garzón
Microprocessor Design with a Direct Bluetooth Connection in 45 nm Technology Using Microwind. LASCAS 2019: 105-108 - [c2]Esteban Garzón
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019: 85-88 - 2016
- [c1]Esteban Garzón
Fast computation of Cramer-Rao Bounds for TOA. LA-CCI 2016: 1-6
Coauthor Index
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last updated on 2024-12-10 20:47 CET by the dblp team
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