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Pierpaolo Palestri
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2020 – today
- 2024
- [j16]Federico Leva
, Claudio Verardo
From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes. IEEE Trans. Biomed. Eng. 71(4): 1115-1126 (2024) - 2023
- [j15]Alessio Cortiula
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 940-951 (2023) - [c27]Federico Leva, Andrea Corna, Paul Werginz, Pierpaolo Palestri, Günter Zeck, Luca Selmi:
Identification of Axon Bendings in Neurons by Multiphysics FEM Simulations of High-Density MEA Extracellular Recordings. SENSORS 2023: 1-4 - [c26]Jacopo Nicolini
Mitigation of Electrical/Ionic Interference in Iontronic Neurostimulation/Neurosensing Platforms: A Simulation Study. SENSORS 2023: 1-4 - 2022
- [j14]Matija Colja
Synchrotron Radiation Study of Gain, Noise, and Collection Efficiency of GaAs SAM-APDs with Staircase Structure. Sensors 22(12): 4598 (2022) - [c25]Federico Leva
Multiphysics Finite-Element Modeling of the Neuron/Electrode Electrodiffusive Interaction. IEEE SENSORS 2022: 1-4 - 2021
- [j13]Francesco Bellando
Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications. Sensors 21(5): 1779 (2021) - [j12]Pierpaolo Palestri
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1392-1401 (2021) - [j11]Hayate Okuhara
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1800-1811 (2021) - [i2]Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi:
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. CoRR abs/2109.01961 (2021) - 2020
- [j10]Davide Menin
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1369-1373 (2020) - [c24]Andrea Cossettini
Ultra-High Frequency (500 MHz) Capacitance Spectroscopy for Nanobiosensing. IEEE SENSORS 2020: 1-4 - [c23]Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. ISCAS 2020: 1-5 - [i1]Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini:
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. CoRR abs/2010.04566 (2020)
2010 – 2019
- 2019
- [c22]Dylan D'Ampolo, Andrea Bandiziol, Davide Menin
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. APCCAS 2019: 225-228 - [c21]Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. MIPRO 2019: 112-116 - 2018
- [j9]Andrea Bandiziol
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1305-1309 (2018) - [c20]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri:
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. ISCAS 2018: 1-5 - [c19]Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. ISCAS 2018: 1-5 - 2017
- [c18]Gia Vinh Luong, Sebastiano Strangio
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM. ESSDERC 2017: 42-45 - 2016
- [c17]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. APCCAS 2016: 321-324 - [c16]Martin Rau, Troels Markussen
Performance study of strained III-V materials for ultra-thin body transistor applications. ESSDERC 2016: 184-187 - [c15]Cem Alper, Jose L. Padilla, Pierpaolo Palestri, Adrian M. Ionescu:
Impact of device geometry of the fin Electron-Hole Bilayer Tunnel FET. ESSDERC 2016: 307-310 - [c14]Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri:
Design of a transmitter for high-speed serial interfaces in automotive micro-controller. MIPRO 2016: 84-88 - 2015
- [j8]Federico Cernoia, Davide Ponton, Pierpaolo Palestri, Peter Thurner, Nicola Da Dalt, Giulio Cecco, Luca Selmi:
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. Int. J. Circuit Theory Appl. 43(6): 709-721 (2015) - [c13]O. Badami, Enrico Caruso
Improved surface roughness modeling and mobility projections in thin film MOSFETs. ESSDERC 2015: 306-309 - [c12]Pierpaolo Palestri, Enrico Caruso
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. MIPRO 2015: 1-8 - [c11]Andrea Cossettini
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. RTSI 2015: 34-38 - 2014
- [c10]Cem Alper, Pierpaolo Palestri, Livio Lattanzio, Jose L. Padilla, Adrian M. Ionescu:
Two dimensional quantum mechanical simulation of low dimensional tunneling devices. ESSDERC 2014: 186-189 - [c9]Sebastiano Strangio
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. ESSDERC 2014: 282-285 - [c8]Stefano Venica, Francesco Driussi
Graphene base transistors with optimized emitter and dielectrics. MIPRO 2014: 33-38 - 2013
- [c7]Alberto Revelant, Pierpaolo Palestri, Patrik Osgnach, Daniel Lizzit
On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices. ESSDERC 2013: 49-52 - [c6]Federico Pittino
On the response of nanoelectrode capacitive biosensors to DNA and PNA strands. IWASI 2013: 40-44 - 2012
- [j7]Yoann Mamy Randriamihaja, Vincent Huard, Xavier Federspiel, Alban Zaka, Pierpaolo Palestri, Denis Rideau, David Roy, Alain Bravaix
Microscopic scale characterization and modeling of transistor degradation under HC stress. Microelectron. Reliab. 52(11): 2513-2520 (2012) - [c5]Daniel Lizzit
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs. ESSDERC 2012: 322-325 - 2011
- [j6]Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Federico Cernoia, Marc Tiebout, Michael Fulde, Pierpaolo Palestri:
LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 467-471 (2011) - 2010
- [j5]Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. Int. J. Circuit Theory Appl. 38(6): 607-629 (2010)
2000 – 2009
- 2009
- [j4]Davide Ponton, Pierpaolo Palestri, David Esseni
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 920-932 (2009) - [c4]Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Marc Tiebout, Michael Fulde, Pierpaolo Palestri:
Assessment of the impact of technology scaling on the performance of LC-VCOs. ESSCIRC 2009: 364-367 - 2008
- [j3]Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi:
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1628-1638 (2008) - [c3]Davide Ponton, Pierpaolo Palestri, David Esseni
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. ISCAS 2008: 2701-2704 - 2007
- [j2]Roberto Nonis, Enzo Palumbo, Pierpaolo Palestri, Luca Selmi:
A Design Methodology for MOS Current-Mode Logic Frequency Dividers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 245-254 (2007) - [c2]Enrico Sangiorgi, Pierpaolo Palestri, David Esseni
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs. ESSCIRC 2007: 48-57 - 2005
- [b1]Pierpaolo Palestri:
Monte-Carlo simulations of hot-carrier effectes and photon-emission in MOS devices. University of Udine, Italy, 2005 - [j1]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. IEEE J. Solid State Circuits 40(6): 1303-1309 (2005) - 2004
- [c1]Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi:
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture. ISCAS (4) 2004: 553-556
Coauthor Index
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