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Scott K. Reynolds
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2010 – 2019
- 2018
- [j21]Bodhisatwa Sadhu
, Tejasvi Anand
A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. IEEE J. Solid State Circuits 53(9): 2488-2499 (2018) - [j20]Wooram Lee
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C. IEEE J. Solid State Circuits 53(9): 2512-2531 (2018) - [c16]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Yahya M. Tousi, Duixian Liu, Scott K. Reynolds, Joakim Hallin, Stefan Sahl, Leonard Rexberg:
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules. CICC 2018: 1-8 - 2017
- [j19]Bodhisatwa Sadhu
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. IEEE J. Solid State Circuits 52(12): 3373-3391 (2017) - [c15]Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia:
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. ISSCC 2017: 128-129 - 2015
- [j18]Xiaoxiong Gu
W-band scalable phased arrays for imaging and communications. IEEE Commun. Mag. 53(4): 196-204 (2015) - 2013
- [j17]Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j16]Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j15]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [c14]Mihai A. T. Sanduleanu
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. CICC 2013: 1-4 - 2012
- [c13]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c12]Jean-Olivier Plouchart, Mihai A. T. Sanduleanu
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC 2012: 1-4 - 2011
- [j14]Alberto Valdes-Garcia, Scott K. Reynolds, Arun Natarajan, Dong Gun Kam, Duixian Liu, Jie-Wei Lai, Yen-Lin Oscar Huang, Ping-Yu Chen, Ming-Da Tsai, Jing-Hong Conan Zhan, Sean Nicolson, Brian A. Floyd
Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications. IEEE Commun. Mag. 49(4): 120-131 (2011) - [j13]Arun Natarajan
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 46(5): 1059-1075 (2011) - [c11]Mihai A. T. Sanduleanu
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI. CICC 2011: 1-4 - 2010
- [j12]Alberto Valdes-Garcia, Sean T. Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Brian A. Floyd
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 45(12): 2757-2773 (2010) - [c10]Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications. ISSCC 2010: 218-219
2000 – 2009
- 2008
- [c9]Yasunao Katayama, Daiju Nakano, Alberto Valdes-Garcia, Troy J. Beukema, Scott K. Reynolds:
Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections. ICME 2008: 513-516 - 2007
- [c8]Yasunao Katayama, Chuck Haymes, Daiju Nakano, Troy J. Beukema, Brian A. Floyd
2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link. CCNC 2007: 12-16 - [c7]Alberto Valdes-Garcia, Scott K. Reynolds, Troy J. Beukema:
Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers. CICC 2007: 639-642 - 2006
- [j11]Scott K. Reynolds, Brian A. Floyd
A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications. IEEE J. Solid State Circuits 41(12): 2820-2831 (2006) - [c6]Brian A. Floyd
A silicon 60GHz receiver and transmitter chipset for broadband communications. ISSCC 2006: 649-658 - 2005
- [j10]Brian A. Floyd
SiGe bipolar transceiver circuits operating at 60 GHz. IEEE J. Solid State Circuits 40(1): 156-167 (2005) - [j9]Sergey V. Rylov
10+ gb/s 90-nm CMOS serial link demo in CBGA package. IEEE J. Solid State Circuits 40(9): 1987-1991 (2005) - [j8]Scott K. Reynolds, Brian A. Floyd
Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband. Proc. IEEE 93(9): 1624-1636 (2005) - [c5]Scott K. Reynolds, Brian A. Floyd
Progress toward a low-cost millimeter-wave silicon radio. CICC 2005: 563-570 - [c4]Ullrich R. Pfeiffer
SiGe transformer matched power amplifier for operation at millimeter-wave frequencies. ESSCIRC 2005: 141-144 - [c3]Anup P. Jose, Keith A. Jenkins, Scott K. Reynolds:
On-Chip Spectrum Analyzer for Analog Built-In Self Test. VTS 2005: 131-136 - 2004
- [j7]Scott K. Reynolds:
A 60-GHz superheterodyne downconversion mixer in silicon-germanium bipolar technology. IEEE J. Solid State Circuits 39(11): 2065-2068 (2004) - [c2]Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd
10+ Gb/s 90nm CMOS serial link demo in CBGA package. CICC 2004: 27-30 - 2003
- [j6]Scott K. Reynolds, Brian A. Floyd
A direct-conversion receiver integrated circuit for WCDMA mobile systems. IBM J. Res. Dev. 47(2-3): 337-354 (2003) - [j5]Scott K. Reynolds, Brian A. Floyd
A direct-conversion receiver IC for WCDMA mobile systems. IEEE J. Solid State Circuits 38(9): 1555-1560 (2003) - 2001
- [j4]Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. IEEE J. Solid State Circuits 36(1): 74-80 (2001)
1990 – 1999
- 1997
- [j3]Scott K. Reynolds:
A DC-DC converter for short-channel CMOS technologies. IEEE J. Solid State Circuits 32(1): 111-113 (1997) - [c1]David J. Frank, Paul M. Solomon, Scott K. Reynolds, John Shin:
Supply and threshold voltage optimization for low power design. ISLPED 1997: 317-322 - 1995
- [j2]Hyun J. Shin, Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner:
Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications. IBM J. Res. Dev. 39(1-2): 83-92 (1995) - [j1]Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner, Michael Immediato, Richard L. Galbraith, Hyun J. Shin:
Digital FIR filters for high speed PRML disk read channels. IEEE J. Solid State Circuits 30(12): 1517-1523 (1995)
Coauthor Index
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