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Peter Buchmann
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2010 – 2019
- 2016
- [c15]Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli:
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC 2016: 56-57 - 2015
- [c14]Hazar Yueksel, Lukas Kull, Andreas Burg
, Matthias Braendli
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC 2015: 148-151 - 2014
- [j11]Pier Andrea Francese
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits 49(11): 2490-2502 (2014) - [c13]Pier Andrea Francese
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC 2014: 435-438 - [c12]Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC 2014: 455-458 - [c11]Martin L. Schmatz, Rik Jongerius, Gero Dittmann
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation. ICASSP 2014: 7505-7509 - [c10]Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. ISSCC 2014: 90-91 - 2013
- [j10]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits 48(12): 3268-3284 (2013) - [c9]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC 2013: 310-311 - [c8]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC 2013: 408-409 - 2012
- [j9]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits 47(4): 897-910 (2012) - [j8]John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(12): 3232-3248 (2012) - [c7]Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli
A 28Gb/s source-series terminated TX in 32nm CMOS SOI. ISSCC 2012: 334-336 - [c6]Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC 2012: 102-103 - 2011
- [c5]Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. ISSCC 2011: 156-158
2000 – 2009
- 2009
- [j7]Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz:
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE J. Solid State Circuits 44(2): 436-449 (2009) - [j6]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz:
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. IEEE J. Solid State Circuits 44(11): 2901-2910 (2009) - 2008
- [j5]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. IEEE J. Solid State Circuits 43(12): 2905-2920 (2008) - [c4]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. ISSCC 2008: 110-111 - 2007
- [c3]Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. ISSCC 2007: 226-598 - [c2]Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. ISSCC 2007: 446-614 - 2006
- [j4]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits 41(4): 954-965 (2006) - 2005
- [j3]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss:
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. IEEE J. Solid State Circuits 40(12): 2700-2712 (2005) - 2001
- [j2]Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. IEEE J. Solid State Circuits 36(1): 74-80 (2001) - 2000
- [j1]Rolf Clauberg
Design Methodology for a Large Communication Chip. IEEE Des. Test Comput. 17(3): 86-94 (2000)
1990 – 1999
- 1998
- [c1]Albert Geukes, Peter Buchmann:
Reproduction of Hypermedia Lectures. WebNet 1998
1980 – 1989
- 1987
- [b1]Peter Buchmann:
GaAs Komponenten der Integrierten Optik für die externe Modulation in optischen Kommunikationssystemen. ETH Zurich, Switzerland, 1987
Coauthor Index
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