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James J. Davis 0001
Person information
- affiliation: Imperial College London, UK
Other persons with the same name
- James J. Davis 0002
— University of Chicago, IL, USA
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2020 – today
- 2023
- [j9]Erwei Wang
Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. 22(6): 105:1-105:19 (2023) - [j8]Erwei Wang
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(4): 57:1-57:25 (2023) - 2022
- [c18]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA 2022: 101-111 - [c17]Marie Auffret, Erwei Wang, James J. Davis:
FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation. FPL 2022: 470 - 2021
- [j7]He Li
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers 70(7): 1074-1080 (2021) - [c16]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys 2021: 37-38 - [i7]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. CoRR abs/2102.04270 (2021) - [i6]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR abs/2112.02346 (2021) - 2020
- [j6]Erwei Wang
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69(12): 1795-1808 (2020) - [j5]He Li
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 516-529 (2020) - [i5]He Li, Ian McInerney
Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR abs/2006.09427 (2020)
2010 – 2019
- 2019
- [j4]Erwei Wang
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [c15]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM 2019: 26-34 - [i4]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i3]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR abs/1904.00938 (2019) - [i2]He Li, James J. Davis, John Wickerson, George A. Constantinides:
ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR abs/1910.00271 (2019) - [i1]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR abs/1910.12625 (2019) - 2018
- [j3]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c14]He Li, James J. Davis, John Wickerson
Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH 2018: 107-114 - [c13]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c12]Erwei Wang, James J. Davis, Peter Y. K. Cheung:
A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM 2018: 223 - [c11]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - [c10]Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi:
An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS 2018: 195-204 - 2017
- [j2]Fei Xia, Ashur Rafiev, Ali Aalsaud, Mohammed A. Noaman Al-Hayanni
Voltage, Throughput, Power, Reliability, and Multicore Scaling. Computer 50(8): 34-45 (2017) - [j1]James J. Davis
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [c9]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - [c8]He Li, James J. Davis, John Wickerson
architect: Arbitrary-precision constant-hardware iterative compute. FPT 2017: 73-79 - 2016
- [c7]James J. Davis, Peter Y. K. Cheung:
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC 2016: 361-368 - [c6]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c5]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - 2015
- [c4]Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi:
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. PATMOS 2015: 103-110 - 2014
- [c3]James J. Davis, Peter Y. K. Cheung:
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM 2014: 103 - [c2]James J. Davis, Peter Y. K. Cheung:
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL 2014: 1-6 - 2013
- [c1]James J. Davis, Peter Y. K. Cheung:
Datapath fault tolerance for parallel accelerators. FPT 2013: 366-369
Coauthor Index
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