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Balaji Narasimham
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2020 – today
- 2024
- [c14]Balaji Narasimham, A-R. Montoya, C. Paone, T. Riehle, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva:
Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. IRPS 2024: 10 - 2023
- [c13]Balaji Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, Mike Smith, Liming Tsau:
Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs. IRPS 2023: 1-4 - 2022
- [c12]Yoni Xiong, Alexandra Feeley, Nicholas J. Pieper, Dennis R. Ball, Balaji Narasimham, John Brockman, N. A. Dodds, S. A. Wender, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva:
Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. IRPS 2022: 7 - 2021
- [c11]Alexandra Feeley, Yoni Xiong, Bharat L. Bhuva, Balaji Narasimham, Shi-Ji Wen, Rita Fung:
Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. IRPS 2021: 1-5 - [c10]Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva:
Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. IRPS 2021: 1-5 - 2020
- [c9]Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva:
Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. IRPS 2020: 1-5
2010 – 2019
- 2019
- [c8]Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Shi-Jie Wen, Richard Wong, Balaji Narasimham, Lloyd W. Massengill:
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. IRPS 2019: 1-5 - [c7]Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva:
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS 2019: 1-4 - 2018
- [c6]H. Zhang, H. Jiang, M. R. Eaker, Kurt J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva:
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. IRPS 2018: 1 - [c5]Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique:
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. IRPS 2018: 4 - [c4]Balaji Narasimham, Tim Wu, Jung K. Wang, Bruce Conway:
Evaluation of the system-level SER performance of gigabit ethernet transceiver devices. IRPS 2018: 4 - [c3]H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva:
Designing soft-error-aware circuits with power and speed optimization. IRPS 2018: 5-1 - 2015
- [c2]Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee
, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed:
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS 2015: 2 - [c1]Nihaar N. Mahatme, Bharat L. Bhuva, Nelson J. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, Balaji Narasimham, A. Shih, Shi-Jie Wen, Rick Wong, N. Tam, M. Shroff, S. Koyoma, A. Oates:
Terrestrial SER characterization for nanoscale technologies: A comparative study. IRPS 2015: 4
Coauthor Index
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