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"A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process ..."

Muhammad M. Khellah et al. (2007)

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DOI: 10.1109/JSSC.2006.888357

access: closed

type: Journal Article

metadata version: 2024-04-26

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  - https://dblp.org/rec/journals/jssc/KhellahSYKHRSTB07
Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 256-Kb Dual-V_CC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007)

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