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"A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop ..."

Satoru Tanoi et al. (1996)

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DOI: 10.1109/4.499724

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - journals/jssc/TanoiTTMU96
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  - https://dblp.org/rec/journals/jssc/TanoiTTMU96
Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi:
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. IEEE J. Solid State Circuits 31(4): 487-493 (1996)

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