• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 46 matches

• 2016
• 
  Laure Abdallah, Mathieu Jan, Jérôme Ermont, Christian Fraboul:
  Poster Abstract: I/O Contention Aware Mapping of Multi-Criticalities Real-Time Applications over Many-Core Architectures. RTAS 2016: 55
• 
  Ankit Agrawal, Gerhard Fohler, Jan Nowotsch, Sascha Uhrig, Michael Paulitsch:
  Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. RTAS 2016: 53
• 
  Ahmed Alhammad, Rodolfo Pellizzoni:
  Trading Cores for Memory Bandwidth in Real-Time Systems. RTAS 2016: 317-327
• 
  Vincenzo Apuzzo, Alessandro Biondi, Giorgio C. Buttazzo:
  OSEK-Like Kernel Support for Engine Control Applications under EDF Scheduling. RTAS 2016: 13-23
• 
  Adnan Bouakaz, Pascal Fradet, Alain Girault:
  Symbolic Buffer Sizing for Throughput-Optimal Scheduling of Dataflow Graphs. RTAS 2016: 199-208
• 
  Carlos A. Rincon C., Albert M. K. Cheng:
  Poster Abstract: Preliminary Performance Evaluation of HEF Scheduling Algorithm. RTAS 2016: 59
• 
  Duc-Hiep Chu, Joxan Jaffar, Rasool Maghareh:
  Precise Cache Timing Analysis via Symbolic Execution. RTAS 2016: 293-304
• 
  Loïc Fejoz, Nicolas Navet, Sakthivel Manikandan Sundharam, Sebastian Altmeyer:
  Demo Abstract: Applications of the CPAL Language to Model, Simulate and Program Cyber-Physical Systems. RTAS 2016: 64
• 
  Hela Guesmi, Belgacem Ben Hedia, Mathieu Jan, Simon Bliudze, Saddek Bensalem:
  Poster Abstract: Towards Correct Transformation: From High-Level Models to Time-Triggered Implementations. RTAS 2016: 52
• 
  Arne Hamann, Dirk Ziegenbein, Simon Kramer, Martin Lukasiewycz:
  Demo Abstract: Demonstration of the FMTV 2016 Timing Verification Challenge. RTAS 2016: 65
• 
  Mohamed Hassan, Hiren D. Patel:
  Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. RTAS 2016: 73-83
• 
  Rafik Henia, Laurent Rioux, Nicolas Sordon:
  Demo Abstract: TEMPO: Integrating Scheduling Analysis in the Industrial Design Practices. RTAS 2016: 63
• 
  Julien Hennig, Hermann von Hasseln, Hassan Mohammad, Stefan Resmerita, Stefan Lukesch, Andreas Naderlinger:
  Poster Abstract: Towards Parallelizing Legacy Embedded Control Software Using the LET Programming Paradigm. RTAS 2016: 51
• 
  Yu Jiang, Yixiao Yang, Han Liu, Hui Kong, Ming Gu, Jia-Guang Sun, Lui Sha:
  From Stateflow Simulation to Verified Implementation: A Verification Approach and A Real-Time Train Controller Design. RTAS 2016: 231-241
• 
  Hany Kashif, Hiren D. Patel:
  Buffer Space Allocation for Real-Time Priority-Aware Networks. RTAS 2016: 255-266
• 
  Namhoon Kim, Bryan C. Ward, Micaiah Chisholm, Cheng-Yang Fu, James H. Anderson, F. Donelson Smith:
  Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning. RTAS 2016: 149-160
• 
  Enagnon Cédric Klikpo, Jad Khatib, Alix Munier Kordon:
  Modeling Multi-Periodic Simulink Systems by Synchronous Dataflow Graphs. RTAS 2016: 209-218
• 
  Philip S. Kurtin, Joost P. H. M. Hausmans, Marco Jan Gerrit Bekooij:
  Combining Offsets with Precedence Constraints to Improve Temporal Analysis of Cyclic Real-Time Streaming Applications. RTAS 2016: 219-230
• 
  Harrison Kurunathan, Ricardo Severino, Anis Koubaa, Eduardo Tovar:
  Poster Abstract: Towards Worst-Case Bounds Analysis of the IEEE 802.15.4e. RTAS 2016: 62
• 
  Adam Lackorzynski, Alexander Warg:
  Demo Abstract: Timing Aware Hardware Virtualization on the L4Re Microkernel Systems. RTAS 2016: 68
• 
  Yonghui Li, Benny Akesson, Kai Lampka, Kees Goossens:
  Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers. RTAS 2016: 85-96
• 
  Jing Li, David Ferry, Shaurya Ahuja, Kunal Agrawal, Christopher D. Gill, Chenyang Lu:
  Mixed-Criticality Federated Scheduling for Parallel Real-Time Tasks. RTAS 2016: 173-184
• 
  Jiaming Lv, Yu Jiang, Xingliang Zou, Albert M. K. Cheng:
  Poster Abstract: Using Linked List in Exact Schedulability Tests for Fixed Priority Scheduling. RTAS 2016: 60
• 
  Sujay Narayana, Pengcheng Huang, Georgia Giannopoulou, Lothar Thiele, R. Venkatesha Prasad:
  Exploring Energy Saving for Mixed-Criticality Systems on Multi-Cores. RTAS 2016: 135-146
• 
  Geoffrey Nelissen, Humberto Carvalho, David Pereira, Eduardo Tovar:
  Demo Abstract: Run-Time Monitoring Environments for Real-Time and Safety Critical Systems. RTAS 2016: 67
• 
  Milos Panic, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
  Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. RTAS 2016: 267-278
• 
  Gaetano Patti, Giovanni Muscato, Nunzio Abbate, Lucia Lo Bello:
  Demo Abstract: A Real-Time Low Datarate Protocol for Cooperative Mobile Robot Teams. RTAS 2016: 70
• 
  Rodolfo Pellizzoni, Heechul Yun:
  Memory Servers for Multicore Systems. RTAS 2016: 97-108
• 
  Quentin Perret, Pascal Maurère, Eric Noulard, Claire Pagetti, Pascal Sainrat, Benoit Triquet:
  Temporal Isolation of Hard Real-Time Applications on Many-Core Processors. RTAS 2016: 37-47
• 
  Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar:
  Poster Abstract: Cache Persistence Aware Response Time Analysis for Fixed Priority Preemptive Systems. RTAS 2016: 57

skipping 16 more matches