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51st MICRO 2018: Fukuoka, Japan
- 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-6240-3
1A: Accelerators
- Anurag Mukkara, Nathan Beckmann, Maleen Abeydeera, Xiaosong Ma, Daniel Sánchez:
Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling. 1-14 - Xuda Zhou, Zidong Du, Qi Guo, Shaoli Liu, Chengsi Liu, Chao Wang, Xuehai Zhou, Ling Li, Tianshi Chen, Yunji Chen
:
Cambricon-S: Addressing Irregularity in Sparse Neural Networks through A Cooperative Software/Hardware Approach. 15-28 - Youwei Zhuo, Jinglei Cheng, Qinyi Luo, Jidong Zhai, Yanzhi Wang, Zhongzhi Luan, Xuehai Qian:
CSE: Parallel Finite State Machines with Convergence Set Enumeration. 29-41 - Dani Voitsechov, Oron Port, Yoav Etsion:
Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays. 42-54 - Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. 55-67
1B: Microarchitecture
- Sizhuo Zhang, Andrew Wright, Thomas Bourgeat
Composable Building Blocks to Open up Processor Design. 68-81 - Hideki Ando:
Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices. 82-94 - Alberto Ros
The Superfluous Load Queue. 95-107 - Almutaz Adileh, David J. Lilja, Lieven Eeckhout:
Architectural Support for Probabilistic Branches. 108-120 - Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. 121-133
2A: ML Accelerators
- Mostafa Mahmoud, Kevin Siu, Andreas Moshovos:
Diffy: a Déjà vu-Free Differential Deep Neural Network Accelerator. 134-147 - Youngeun Kwon
Beyond the Memory Wall: A Case for Memory-Centric HPC System for Deep Learning. 148-161 - Xingyao Zhang
Towards Memory Friendly Long-Short Term Memory Networks (LSTMs) on Mobile GPUs. 162-174 - Youjie Li, Jongse Park, Mohammad Alian
A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks. 175-188 - Chunhua Deng, Siyu Liao, Yi Xie, Keshab K. Parhi
PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices. 189-202
2B: Compilers and Programming Languages
- Po-An Tsai, Yee Ling Gan, Daniel Sánchez:
Rethinking the Memory Hierarchy for Modern Languages. 203-216 - Mark C. Jeffrey
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. 217-230 - Sam Silvestro, Hongyu Liu, Tong Zhang, Changhee Jung, Dongyoon Lee
Sampler: PMU-Based Sampling to Detect Memory Errors Latent in Production Software. 231-244 - Steve Margerm, Amirali Sharifian, Apala Guha, Arrvindh Shriraman, Gilles Pokam:
TAPAS: Generating Parallel Accelerators from Parallel Programs. 245-257 - Qingrui Liu, Joseph Izraelevitz, Se Kwon Lee, Michael L. Scott
iDO: Compiler-Directed Failure Atomicity for Nonvolatile Memory. 258-270
3A: Memory Systems - I
- Srikant Bharadwaj, Guilherme Cox
Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects. 271-284 - Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt:
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. 285-297 - Yaohua Wang, Arash Tavakkol, Lois Orosa
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration. 298-311 - Tri Minh Nguyen, Adi Fuchs, David Wentzlaff:
CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores. 312-325 - Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. 326-338
3B: GPGPU/GPU
- Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David W. Nellans, Oreste Villa:
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems. 339-351 - Seunghee Shin, Michael LeBeane, Yan Solihin, Arkaprava Basu:
Neighborhood-Aware Address Translation for Irregular GPU Applications. 352-363 - Yunho Oh
FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput. 364-376 - Farzad Khorasani, Hodjat Asghari Esfeden, Nael B. Abu-Ghazaleh
In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization. 377-389 - An Zou, Jingwen Leng, Xin He, Yazhou Zu, Christopher D. Gill, Vijay Janapa Reddi, Xuan Zhang
Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs. 390-402
4A: Security - I
- Mao Ye
Osiris: A Low-Cost Mechanism to Enable Restoration of Secure Non-Volatile Memories. 403-415 - Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories. 416-427 - Mengjia Yan
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy. 428-441 - Pengfei Zuo, Yu Hua, Ming Zhao
Improving the Performance and Endurance of Encrypted Non-Volatile Main Memory through Deduplicating Writes. 442-454
4B: Storage Systems & Technologies
- Joonsung Kim, Pyeongsu Park, Jaehyung Ahn, Jihun Kim, Jong Kim, Jangwoo Kim:
SSDcheck: Timely and Accurate Prediction of Irregular Behaviors in Black-Box SSDs. 455-468 - Donghyun Gouk, Miryeong Kwon, Jie Zhang, Sungjoon Koh, Wonil Choi, Nam Sung Kim, Mahmut T. Kandemir, Myoungsoo Jung:
Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources. 469-481 - Wonil Choi, Myoungsoo Jung, Mahmut T. Kandemir:
Invalid Data-Aware Coding to Enhance the Read Performance of High-Density Flash Memories. 482-493 - Xing Hu, Matheus Ogleari, Jishen Zhao, Shuangchen Li, Abanti Basak, Yuan Xie:
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network. 494-506
5A: Memory Systems - II
- Tri Minh Nguyen, David Wentzlaff:
PiCL: A Software-Transparent, Persistent Cache Log for Nonvolatile Main Memory. 507-519 - Jungi Jeong, Chang Hyun Park
Efficient Hardware-Assisted Logging with Asynchronous and Direct-Update for Persistent Memory. 520-532 - Jagadish B. Kotra, Haibo Zhang, Alaa R. Alameldeen, Chris Wilkerson, Mahmut T. Kandemir:
CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System. 533-545 - Esha Choukse, Mattan Erez
Compresso: Pragmatic Main Memory Compression. 546-558 - Amna Shahab, Mingcan Zhu, Artemiy Margaritov
Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers. 559-572
5B: Measurement, Modeling, and Simulation
- Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. 573-585 - Hanhwi Jang, Jae-Eon Jo, Jaewon Lee, Jangwoo Kim:
RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors. 586-599 - Joshua San Miguel
The EH Model: Early Design Space Exploration of Intermittent Processor Architectures. 600-612 - Yirong Lv, Bin Sun, Qingyi Luo, Jing Wang, Zhibin Yu, Xuehai Qian:
CounterMiner: Mining Big Performance Data from Hardware Counters. 613-626 - Shenghsun Cho, Amoghavarsha Suresh, Tapti Palit, Michael Ferdman, Nima Honarmand:
Taming the Killer Microsecond. 627-640
6A: Near Memory Computing
- Po-An Tsai, Changping Chen, Daniel Sánchez:
Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies. 641-654 - Jiawen Liu, Hengyu Zhao, Matheus A. Ogleari, Dong Li, Jishen Zhao:
Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach. 655-668 - Haiyu Mao, Mingcong Song, Tao Li, Yuting Dai, Jiwu Shu:
LerGAN: A Zero-Free, Low Data Movement and PIM-Based GAN Architecture. 669-681 - Byungchul Hong, Yeonju Ro, John Kim
Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture. 682-695 - Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. 696-709
6B: Near Memory Computing
- Da Zhang, Vilas Sridharan, Xun Jian
Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs. 710-723 - Behzad Salami
Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories. 724-736 - Emre Ozer, Balaji Venu, Xabier Iturbe
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. 737-748 - Bin Nie, Lishan Yang, Adwait Jog, Evgenia Smirni
Fault Site Pruning for Practical Reliability Analysis of GPGPU Applications. 749-761 - Michael B. Sullivan, Siva Kumar Sastry Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler:
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection. 762-774
7: Best Papers
- Moinuddin K. Qureshi:
CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping. 775-787 - Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications. 788-801 - Mohammad Alian
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network. 802-814 - Rui Zhang, Calvin Deutschbein
End-to-End Automated Exploit Generation for Validating the Security of Processor Designs. 815-827
8A: Non-Conventional Architectures
- Yongshan Ding
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures. 828-840 - Sumitha George, Minli Julie Liao, Huaipan Jiang, Jagadish B. Kotra, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan:
MDACache: Caching for Multi-Dimensional-Access Memories. 841-854 - Ananda Samajdar, Parth Mannan, Kartikay Garg, Tushar Krishna:
GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware. 855-866
8B: Mobile and Embedded Architectures
- Prasanna Venkatesh Rengasamy, Haibo Zhang, Shulin Zhao, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das:
CritICs Critiquing Criticality in Mobile Apps. 867-880 - Moumita Dey
EMPROF: Memory Profiling Via EM-Emanation in IoT and Hand-Held Devices. 881-893 - Behzad Boroujerdian, Hasan Genc, Srivatsan Krishnan, Wenzhi Cui, Aleksandra Faust
MAVBench: Micro Aerial Vehicle Benchmarking. 894-907
9A: Domain-Specific Architectures
- Hongyuan Liu
Architectural Support for Efficient Large-Scale Automata Processing. 908-920 - Kevin Angstadt
ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. 921-932 - Kartik Hegde, Rohit Agrawal, Yulun Yao, Christopher W. Fletcher:
Morph: Flexible Acceleration for 3D CNN-Based Video Understanding. 933-946
9B: Security-II
- Caroline Trippel, Daniel Lustig, Margaret Martonosi:
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests. 947-960 - Xian Zhang, Guangyu Sun, Peichen Xie, Chao Zhang, Yannan Liu, Lingxiao Wei, Qiang Xu
Shadow Block: Accelerating ORAM Accesses with Data Duplication. 961-973 - Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer:
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. 974-987
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