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Yuan Xie 0001
Person information
- affiliation: Alibaba DAMO Academy
- affiliation (former): University of California at Santa Barbara, CA, USA
- affiliation (2003 - 2013): Pennsylvania State University, Philadelphia, PA, USA
- affiliation (PhD 2002): Princeton University, Princeton, NJ, USA
Other persons with the same name
- Yuan Xie — disambiguation page
- Yuan Xie 0002 — Shanghai Jiao Tong University, China
- Yuan Xie 0003 — California Institute of Technology, Center for Computational Regulatory Genomics, CA, USA
- Yuan Xie 0004 — Sun Yat-sen University, Guangzhou, China
- Yuan Xie 0005 — Indiana University Bloomington, USA
- Yuan Xie 0006
— East China Normal University, Shanghai, China (and 2 more)
- Yuan Xie 0007
- Yuan Xie 0008
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2020 – today
- 2024
- [j166]Yiquan Chen
Optimizing NVMe Storage for Large-Scale Deployment: Key Technologies and Strategies in Alibaba Cloud. IEEE Micro 44(5): 47-56 (2024) - [j165]Nan Wu
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-42 (2024) - [c357]Zhaodong Chen
EVT: Accelerating Deep Learning Training with Epilogue Visitor Tree. ASPLOS (3) 2024: 301-316 - [i80]Meng Wu, Mingyu Yan, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie:
A Comprehensive Survey on GNN Characterization. CoRR abs/2408.01902 (2024) - 2023
- [j164]Nan Wu
A Survey of Machine Learning for Computer Architecture and Systems. ACM Comput. Surv. 55(3): 54:1-54:39 (2023) - [j163]Fengbin Tu
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits 58(1): 243-255 (2023) - [j162]Fengbin Tu
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits 58(6): 1798-1809 (2023) - [j161]Guiming Wu
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption. IEEE Micro 43(5): 88-96 (2023) - [j160]Haiyang Lin
A Comprehensive Survey on Distributed Training of Graph Neural Networks. Proc. IEEE 111(12): 1572-1606 (2023) - [j159]Ling Liang, Jilan Lin, Zheng Qu, Ishtiyaque Ahmad, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie:
SPG: Structure-Private Graph Database via SqueezePIR. Proc. VLDB Endow. 16(7): 1615-1628 (2023) - [j158]Fengbin Tu
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 109-121 (2023) - [j157]Nan Wu
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 900-913 (2023) - [j156]Bizhao Shi
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3910-3924 (2023) - [j155]Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4112-4125 (2023) - [j154]Yiqi Wang
SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 214-227 (2023) - [j153]Ling Liang
Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient. IEEE Trans. Neural Networks Learn. Syst. 34(5): 2569-2583 (2023) - [j152]Lei Deng
Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization. IEEE Trans. Neural Networks Learn. Syst. 34(6): 2791-2805 (2023) - [j151]Yanhong Wang
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34(9): 2598-2614 (2023) - [c356]Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao:
Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. ASPLOS (2) 2023: 747-761 - [c355]Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. DAC 2023: 1-6 - [c354]Ao Ren, Yuhao Wang, Tao Zhang, Jiaxing Shi, Duo Liu, Xianzhang Chen
HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference. DAC 2023: 1-6 - [c353]Nan Wu
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. DAC 2023: 1-6 - [c352]Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie:
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. ICCAD 2023: 1-9 - [c351]Siqi Li
ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification. ISCA 2023: 58:1-58:14 - [c350]Chen Bai
ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. MICRO 2023: 268-282 - [c349]Shulin Zeng
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search. MICRO 2023: 283-296 - [c348]Guyue Huang
RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration. MICRO 2023: 338-352 - [c347]Zheng Qu
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. MICRO 2023: 452-464 - [c346]Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie:
ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs. MLSys 2023 - [c345]Zhaodong Chen, Zheng Qu, Yuying Quan, Liu Liu
Dynamic N: M Fine-Grained Structured Sparse Attention Mechanism. PPoPP 2023: 369-379 - [i79]Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie:
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. CoRR abs/2303.08256 (2023) - [i78]Yiquan Chen
High-performance and Scalable Software-based NVMe Virtualization Mechanism with I/O Queues Passthrough. CoRR abs/2304.05148 (2023) - [i77]Yuanwei Fang, Zihao Liu, Yanheng Lu, Jiawei Liu
NPS: A Framework for Accurate Program Sampling Using Graph Neural Network. CoRR abs/2304.08880 (2023) - [i76]Jianyu Xu, Hanwen Zhang, Ling Liang, Lei Deng, Yuan Xie, Guoqi Li:
NP-Hardness of Tensor Network Contraction Ordering. CoRR abs/2310.06140 (2023) - 2022
- [j150]Linyong Huang
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10: 46796-46807 (2022) - [j149]Zhaoyang Du
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access 10: 79237-79248 (2022) - [j148]Zhaoyang Du
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access 10: 85960-85974 (2022) - [j147]Xinfeng Xie
MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures. IEEE Comput. Archit. Lett. 21(1): 1-4 (2022) - [j146]Mingyu Yan
Characterizing and Understanding HGNNs on GPUs. IEEE Comput. Archit. Lett. 21(2): 69-72 (2022) - [j145]Linyong Huang, Zhe Zhang, Zhaoyang Du
EPQuant: A Graph Neural Network compression approach based on product quantization. Neurocomputing 503: 49-61 (2022) - [j144]Jeong-Jun Lee
SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 18(4): 68:1-68:23 (2022) - [j143]Zhaodong Chen
A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks. IEEE Trans. Pattern Anal. Mach. Intell. 44(1): 13-31 (2022) - [j142]Xuanle Ren, Le Su, Zhen Gu
HEDA: Multi-Attribute Unbounded Aggregation over Homomorphically Encrypted Database. Proc. VLDB Endow. 16(4): 601-614 (2022) - [j141]Bangyan Wang
Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture. IEEE Trans. Computers 71(2): 266-281 (2022) - [j140]Gongjian Sun
Multi-Node Acceleration for Large-Scale GCNs. IEEE Trans. Computers 71(12): 3140-3152 (2022) - [j139]Liu Liu
Dynamic Sparse Attention for Scalable Transformer Acceleration. IEEE Trans. Computers 71(12): 3165-3178 (2022) - [j138]Xing Hu
A Systematic View of Model Leakage Risks in Deep Neural Network Systems. IEEE Trans. Computers 71(12): 3254-3267 (2022) - [j137]Zheng Qu
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 372-385 (2022) - [j136]Xiaobing Chen
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 936-949 (2022) - [j135]Yuke Wang
STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1358-1370 (2022) - [j134]Ling Liang
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4782-4796 (2022) - [c344]Nan Wu
LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. ASAP 2022: 11-18 - [c343]Zheng Qu
DOTA: detect and omit weak attentions for scalable transformer acceleration. ASPLOS 2022: 14-26 - [c342]Gushu Li
Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels. ASPLOS 2022: 554-569 - [c341]Bangyan Wang
A one-for-all and o(v log(v ))-cost solution for parallel merge style operations on sorted key-value arrays. ASPLOS 2022: 669-682 - [c340]Zejiang Hou, Minghai Qin, Fei Sun, Xiaolong Ma, Kun Yuan, Yi Xu, Yen-Kuang Chen, Rong Jin, Yuan Xie, Sun-Yuan Kung:
CHEX: CHannel EXploration for CNN Model Compression. CVPR 2022: 12277-12288 - [c339]Nan Wu
High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. DAC 2022: 49-54 - [c338]Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang:
Heuristic adaptability to input dynamics for SpMM on CPUs. DAC 2022: 595-600 - [c337]Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan
Alleviating datapath conflicts and design centralization in graph analytics acceleration. DAC 2022: 901-906 - [c336]Guyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie:
Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning. DAC 2022: 1153-1158 - [c335]Ling Liang, Zhaodong Chen, Lei Deng
Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU. DATE 2022: 658-663 - [c334]Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie:
2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. ICCAD 2022: 95:1-95:7 - [c333]Nan Wu
AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects. ICCD 2022: 207-214 - [c332]Xiaolong Ma, Minghai Qin, Fei Sun, Zejiang Hou, Kun Yuan, Yi Xu, Yanzhi Wang, Yen-Kuang Chen, Rong Jin, Yuan Xie:
Effective Model Sparsification by Scheduled Grow-and-Prune Methods. ICLR 2022 - [c331]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS 2022: 483-490 - [c330]Minghai Qin, Tianyun Zhang, Fei Sun, Yen-Kuang Chen, Makan Fardad, Yanzhi Wang, Yuan Xie:
Compact Multi-level Sparse Neural Networks with Input Independent Dynamic Rerouting. ICTAI 2022: 555-562 - [c329]Xin Liu, Mingyu Yan, Lei Deng, Guoqi Li, Xiaochun Ye, Dongrui Fan, Shirui Pan, Yuan Xie:
Survey on Graph Neural Network Acceleration: An Algorithmic Perspective. IJCAI 2022: 5521-5529 - [c328]Jilan Lin, Ling Liang, Zheng Qu, Ishtiyaque Ahmad, Liu Liu
INSPIRE: in-storage private information retrieval via protocol and architecture co-design. ISCA 2022: 102-115 - [c327]Guohao Dai, Zhenhua Zhu, Tianyu Fu
DIMMining: pruning-efficient and parallel graph mining on near-memory-computing. ISCA 2022: 130-145 - [c326]Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, Yuan Xie:
A synthesis framework for stitching surface code with superconducting quantum devices. ISCA 2022: 337-350 - [c325]Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA 2022: 946-961 - [c324]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - [c323]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC 2022: 1-3 - [c322]Haozhe Zhu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - [c321]Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC 2022: 466-468 - [c320]Wenqin Huangfu, Krishna T. Malladi, Andrew Chang, Yuan Xie:
BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support. MICRO 2022: 727-743 - [c319]Anbang Wu, Hezi Zhang, Gushu Li, Alireza Shabani, Yuan Xie, Yufei Ding:
AutoComm: A Framework for Enabling Efficient Communication in Distributed Quantum Programs. MICRO 2022: 1027-1041 - [c318]Hengrui Zhang, Zhongming Yu, Guohao Dai, Guyue Huang, Yufei Ding, Yuan Xie, Yu Wang:
Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective. MLSys 2022 - [c317]Ling Liang, Kaidi Xu, Xing Hu, Lei Deng, Yuan Xie:
Toward Robust Spiking Neural Network Against Adversarial Perturbation. NeurIPS 2022 - [c316]Boyuan Feng, Tianqi Tang, Yuke Wang, Zhaodong Chen, Zheng Wang, Shu Yang, Yuan Xie, Yufei Ding:
Faith: An Efficient Framework for Transformer Verification on GPUs. USENIX ATC 2022: 167-182 - [i75]Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao:
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing. CoRR abs/2201.06848 (2022) - [i74]Nan Wu, Jiwon Lee, Yuan Xie, Cong Hao:
Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information. CoRR abs/2201.08455 (2022) - [i73]Xin Liu, Mingyu Yan, Lei Deng, Guoqi Li, Xiaochun Ye, Dongrui Fan, Shirui Pan, Yuan Xie:
Survey on Graph Neural Network Acceleration: An Algorithmic Perspective. CoRR abs/2202.04822 (2022) - [i72]Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang:
Heuristic Adaptability to Input Dynamics for SpMM on GPUs. CoRR abs/2202.08556 (2022) - [i71]Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie:
Alleviating Datapath Conflicts and Design Centralization in Graph Analytics Acceleration. CoRR abs/2202.11343 (2022) - [i70]Zhaodong Chen, Yuying Quan, Zheng Qu, Liu Liu, Yufei Ding, Yuan Xie:
Dynamic N: M Fine-grained Structured Sparse Attention Mechanism. CoRR abs/2203.00091 (2022) - [i69]Guyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie:
Shfl-BW: Accelerating Deep Neural Network Inference with Tensor-Core Aware Weight Pruning. CoRR abs/2203.05016 (2022) - [i68]Zejiang Hou, Minghai Qin, Fei Sun, Xiaolong Ma, Kun Yuan, Yi Xu, Yen-Kuang Chen, Rong Jin, Yuan Xie, Sun-Yuan Kung:
CHEX: CHannel EXploration for CNN Model Compression. CoRR abs/2203.15794 (2022) - [i67]Ling Liang, Kaidi Xu, Xing Hu, Lei Deng
Toward Robust Spiking Neural Network Against Adversarial Perturbation. CoRR abs/2205.01625 (2022) - [i66]Zihao Zhao, Yanhong Wang, Qiaosha Zou, Tie Xu, Fangbo Tao, Jiansong Zhang, Xiaoan Wang
The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. CoRR abs/2206.01910 (2022) - [i65]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie:
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR abs/2206.06611 (2022) - [i64]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie:
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR abs/2206.07244 (2022) - [i63]Tianqi Tang, Yuan Xie:
Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies. CoRR abs/2206.07308 (2022) - [i62]Gongjian Sun, Mingyu Yan, Duo Wang, Han Li, Wenming Li, Xiaochun Ye, Dongrui Fan, Yuan Xie:
Multi-node Acceleration for Large-scale GCNs. CoRR abs/2207.07258 (2022) - [i61]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR abs/2207.13848 (2022) - [i60]Mingyu Yan, Mo Zou, Xiaocheng Yang, Wenming Li, Xiaochun Ye, Dongrui Fan
Characterizing and Understanding HGNNs on GPUs. CoRR abs/2208.04758 (2022) - [i59]Zejiang Hou, Fei Sun, Yen-Kuang Chen, Yuan Xie, Sun-Yuan Kung:
MILAN: Masked Image Pretraining on Language Assisted Representation. CoRR abs/2208.06049 (2022) - [i58]Boyuan Feng, Tianqi Tang, Yuke Wang, Zhaodong Chen, Zheng Wang, Shu Yang, Yuan Xie, Yufei Ding:
Faith: An Efficient Framework for Transformer Verification on GPUs. CoRR abs/2209.12708 (2022) - [i57]Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie:
Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. CoRR abs/2210.16691 (2022) - [i56]Haiyang Lin, Mingyu Yan, Xiaochun Ye, Dongrui Fan
A Comprehensive Survey on Distributed Training of Graph Neural Networks. CoRR abs/2211.05368 (2022) - 2021
- [j133]Han Li
Hardware Acceleration for GCNs via Bidirectional Fusion. IEEE Comput. Archit. Lett. 20(1): 66-69 (2021) - [j132]Liu Liu
Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures. Computer 54(4): 14-25 (2021) - [j131]Yuan Xie
Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020). IEEE Des. Test 38(2): 100-101 (2021) - [j130]Jiayi Yang, Lei Deng
Training and inference for integer-based semantic segmentation network. Neurocomputing 454: 101-112 (2021) - [j129]Hengnu Chen, Lei Deng
Tensor train decomposition for solving large-scale linear equations. Neurocomputing 464: 203-217 (2021) - [j128]Fengbin Tu
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. IEEE J. Solid State Circuits 56(2): 658-673 (2021) - [j127]Fengbin Tu
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". IEEE J. Solid State Circuits 56(9): 2895 (2021) - [j126]Ling Liang
Fast Search of the Optimal Contraction Sequence in Tensor Networks. IEEE J. Sel. Top. Signal Process. 15(3): 574-586 (2021) - [j125]Xing Hu
Practical Attacks on Deep Neural Networks by Memory Trojaning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1230-1243 (2021) - [j124]Peng Gu
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1586-1599 (2021) - [j123]Jilan Lin
Rescuing RRAM-Based Computing From Static and Dynamic Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2049-2062 (2021) - [j122]Ing-Chao Lin
A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1413-1417 (2021) - [j121]Zhaodong Chen
Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation. IEEE Trans. Neural Networks Learn. Syst. 32(1): 348-362 (2021) - [j120]Nan Wu
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning. ACM Trans. Design Autom. Electr. Syst. 26(2): 11:1-11:27 (2021) - [c315]Yuke Wang, Boyuan Feng, Gushu Li, Georgios Tzimpragos
TiAcc: Triangle-inequality based Hardware Accelerator for K-means on FPGAs. CCGRID 2021: 133-142 - [c314]Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie:
SEALing Neural Network Models in Encrypted Deep Learning Accelerators. DAC 2021: 1255-1260 - [c313]Nan Wu
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. ACM Great Lakes Symposium on VLSI 2021: 39-44 - [c312]Xinfeng Xie, Zheng Liang
SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator. HPCA 2021: 570-583 - [c311]Tianqi Tang, Sheng Li, Lifeng Nai, Norman P. Jouppi, Yuan Xie:
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. HPCA 2021: 841-853 - [c310]Hussam Amrouch, Jian-Jia Chen
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c309]Jilan Lin, Shuangchen Li, Yufei Ding, Yuan Xie:
Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications. ICCAD 2021: 1-9 - [c308]Abanti Basak, Zheng Qu, Jilan Lin
Improving Streaming Graph Processing Performance using Input Knowledge. MICRO 2021: 1036-1050 - [c307]Liu Liu
ENMC: Extreme Near-Memory Classification via Approximate Screening. MICRO 2021: 1309-1322 - [c306]Gushu Li, Anbang Wu, Yunong Shi, Ali Javadi-Abhari, Yufei Ding, Yuan Xie:
On the Co-Design of Quantum Software and Hardware. NANOCOM 2021: 15:1-15:7 - [c305]Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding:
GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs. OSDI 2021: 515-531 - [c304]Boyuan Feng, Yuke Wang, Guoyang Chen, Weifeng Zhang, Yuan Xie, Yufei Ding:
EGEMM-TC: accelerating scientific computing on tensor cores with extended precision. PPoPP 2021: 278-291 - [c303]Zhaodong Chen, Zheng Qu, Liu Liu
Efficient tensor core-based GPU kernels for structured sparsity under reduced precision. SC 2021: 78 - [c302]Boyuan Feng, Yuke Wang, Gushu Li, Yuan Xie, Yufei Ding:
Palleon: A Runtime System for Efficient Video Processing toward Dynamic Class Skew. USENIX ATC 2021: 427-441 - [i55]Nan Wu
A Survey of Machine Learning for Computer Architecture and Systems. CoRR abs/2102.07952 (2021) - [i54]Nan Wu
IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. CoRR abs/2102.08138 (2021) - [i53]Eren Kurshan, Hai Helen Li, Mingoo Seok, Yuan Xie:
A Case for 3D Integrated System Design for Neuromorphic Computing & AI Applications. CoRR abs/2103.04852 (2021) - [i52]Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie:
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. CoRR abs/2103.06653 (2021) - [i51]Xiaolong Ma, Minghai Qin, Fei Sun, Zejiang Hou, Kun Yuan, Yi Xu, Yanzhi Wang, Yen-Kuang Chen, Rong Jin, Yuan Xie:
Effective Model Sparsification by Scheduled Grow-and-Prune Methods. CoRR abs/2106.09857 (2021) - [i50]Guyue Huang, Guohao Dai, Yu Wang, Yufei Ding, Yuan Xie:
Efficient Sparse Matrix Kernels based on Adaptive Workload-Balancing and Parallel-Reduction. CoRR abs/2106.16064 (2021) - [i49]Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie:
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks. CoRR abs/2107.11746 (2021) - [i48]Nan Wu, Huake He, Yuan Xie, Pan Li, Cong Hao:
Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation. CoRR abs/2109.06265 (2021) - [i47]Hengrui Zhang, Zhongming Yu, Guohao Dai, Guyue Huang, Yufei Ding, Yuan Xie, Yu Wang:
Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective. CoRR abs/2110.09524 (2021) - [i46]Liu Liu, Zheng Qu, Zhaodong Chen, Yufei Ding, Yuan Xie:
Transformer Acceleration with Dynamic Sparse Attention. CoRR abs/2110.11299 (2021) - [i45]Anbang Wu, Gushu Li, Yufei Ding, Yuan Xie:
Mitigating Noise-Induced Gradient Vanishing in Variational Quantum Algorithm Training. CoRR abs/2111.13209 (2021) - [i44]Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yuan Xie, Yufei Ding:
QECV: Quantum Error Correction Verification. CoRR abs/2111.13728 (2021) - [i43]Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, Yuan Xie:
Mapping Surface Code to Superconducting Quantum Processors. CoRR abs/2111.13729 (2021) - [i42]Anbang Wu, Gushu Li, Yuke Wang, Boyuan Feng, Yufei Ding, Yuan Xie:
Towards Efficient Ansatz Architecture for Variational Quantum Algorithms. CoRR abs/2111.13730 (2021) - [i41]Fei Sun, Minghai Qin, Tianyun Zhang, Xiaolong Ma, Haoran Li, Junwen Luo, Zihao Zhao, Yen-Kuang Chen, Yuan Xie:
Load-balanced Gather-scatter Patterns for Sparse Deep Neural Networks. CoRR abs/2112.10898 (2021) - [i40]Minghai Qin, Tianyun Zhang, Fei Sun, Yen-Kuang Chen, Makan Fardad, Yanzhi Wang, Yuan Xie:
Compact Multi-level Sparse Neural Networks with Input Independent Dynamic Rerouting. CoRR abs/2112.10930 (2021) - 2020
- [j119]Mingyu Yan
Characterizing and Understanding GCNs on GPU. IEEE Comput. Archit. Lett. 19(1): 22-25 (2020) - [j118]Peng Gu
NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices. IEEE Comput. Archit. Lett. 19(1): 76-79 (2020) - [j117]Eren Kurshan, Hai Li, Mingoo Seok, Yuan Xie:
A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications. Int. J. Semantic Comput. 14(4): 457-475 (2020) - [j116]Lei Deng
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation. IEEE J. Solid State Circuits 55(8): 2228-2246 (2020) - [j115]Lei Deng
Rethinking the performance comparison between SNNS and ANNS. Neural Networks 121: 294-307 (2020) - [j114]Yukuan Yang, Lei Deng
Training high-performance and large-scale deep neural networks with full 8-bit integers. Neural Networks 125: 70-82 (2020) - [j113]Weihua He
Comparing SNNs and RNNs on neuromorphic vision datasets: Similarities and differences. Neural Networks 132: 108-120 (2020) - [j112]Gushu Li
Projection-based runtime assertions for testing and debugging Quantum programs. Proc. ACM Program. Lang. 4(OOPSLA): 150:1-150:29 (2020) - [j111]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri:
Scanning the Issue. Proc. IEEE 108(4): 483-484 (2020) - [j110]Lei Deng
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey. Proc. IEEE 108(4): 485-532 (2020) - [j109]Xinfeng Xie
NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. ACM Trans. Archit. Code Optim. 17(4): 31:1-31:25 (2020) - [j108]Yijin Guan
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers 69(7): 931-943 (2020) - [j107]Lei Deng
SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 117-130 (2020) - [c301]Ao Ren, Tao Zhang, Yuhao Wang, Sheng Lin, Peiyan Dong, Yen-Kuang Chen, Yuan Xie, Yanzhi Wang:
DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks. AAAI 2020: 5495-5502 - [c300]Xing Hu, Ling Liang, Shuangchen Li, Lei Deng
DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints. ASPLOS 2020: 385-399 - [c299]Gushu Li, Yufei Ding, Yuan Xie:
Towards Efficient Superconducting Quantum Processor Architecture Design. ASPLOS 2020: 1031-1045 - [c298]Gushu Li, Yufei Ding, Yuan Xie:
Eliminating Redundant Computation in Noisy Quantum Computing Simulation. DAC 2020: 1-6 - [c297]Fei Sun, Minghai Qin, Tianyun Zhang, Liu Liu
INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware. DAC 2020: 1-6 - [c296]Maohua Zhu, Yuan Xie:
Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization. DAC 2020: 1-6 - [c295]Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI 2020: 83-88 - [c294]Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium 2020: 1-19 - [c293]Mingyu Yan, Lei Deng
HyGCN: A GCN Accelerator with Hybrid Architecture. HPCA 2020: 15-29 - [c292]Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators. HPCA 2020: 556-569 - [c291]Wenqin Huangfu, Krishna T. Malladi, Shuangchen Li, Peng Gu, Yuan Xie:
NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting. ICCAD 2020: 28:1-28:9 - [c290]Zhaodong Chen, Mingyu Yan, Maohua Zhu, Lei Deng
fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU. ICCAD 2020: 60:1-60:9 - [c289]Liu Liu, Lei Deng, Zhaodong Chen, Yuke Wang, Shuangchen Li, Jingwei Zhang, Yihua Yang, Zhenyu Gu, Yufei Ding, Yuan Xie:
Boosting Deep Neural Network Efficiency with Dual-Module Inference. ICML 2020: 6205-6215 - [c288]Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA 2020: 52-64 - [c287]Peng Gu
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. ISCA 2020: 804-817 - [c286]Weitao Li, Pengfei Xu, Yang Zhao
Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain. ISCA 2020: 832-845 - [c285]Yang Zhao
SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation. ISCA 2020: 954-967 - [c284]Abanti Basak, Jilan Lin
SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads. ISPASS 2020: 12-23 - [c283]Liu Liu
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. MICRO 2020: 738-750 - [i39]Zhaodong Chen, Lei Deng, Bangyan Wang, Guoqi Li, Yuan Xie:
A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks. CoRR abs/2001.00254 (2020) - [i38]Ling Liang, Xing Hu, Lei Deng, Yujie Wu, Guoqi Li, Yufei Ding, Peng Li, Yuan Xie:
Exploring Adversarial Attack in Spiking Neural Networks with Spike-Compatible Gradient. CoRR abs/2001.01587 (2020) - [i37]Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie:
HyGCN: A GCN Accelerator with Hybrid Architecture. CoRR abs/2001.02514 (2020) - [i36]Nan Wu, Adrien F. Vincent, Dmitri B. Strukov, Yuan Xie:
Memristor Hardware-Friendly Reinforcement Learning. CoRR abs/2001.06930 (2020) - [i35]Mingyu Yan, Zhaodong Chen, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie:
Characterizing and Understanding GCNs on GPU. CoRR abs/2001.10160 (2020) - [i34]Fei Sun, Minghai Qin, Tianyun Zhang, Liu Liu, Yen-Kuang Chen, Yuan Xie:
Computation on Sparse Neural Networks: an Inspiration for Future Hardware. CoRR abs/2004.11946 (2020) - [i33]Weitao Li, Pengfei Xu, Yang Zhao, Haitong Li, Yuan Xie, Yingyan Lin:
TIMELY: Pushing Data Movements and Interfaces in PIM Accelerators Towards Local and in Time Domain. CoRR abs/2005.01206 (2020) - [i32]Weihua He, Yujie Wu, Lei Deng, Guoqi Li, Haoyu Wang, Yang Tian, Wei Ding, Wenhui Wang, Yuan Xie:
Comparing SNNs and RNNs on Neuromorphic Vision Datasets: Similarities and Differences. CoRR abs/2005.02183 (2020) - [i31]Yang Zhao, Xiaohan Chen, Yue Wang, Chaojian Li, Haoran You, Yonggan Fu, Yuan Xie, Zhangyang Wang, Yingyan Lin:
SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation. CoRR abs/2005.03403 (2020) - [i30]Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding:
GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs. CoRR abs/2006.06608 (2020) - [i29]Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie:
SEALing Neural Network Models in Secure Deep Learning Accelerators. CoRR abs/2008.03752 (2020) - [i28]Xiaobing Chen, Yuke Wang, Xinfeng Xie, Xing Hu, Abanti Basak, Ling Liang, Mingyu Yan, Lei Deng, Yufei Ding, Zidong Du, Yunji Chen, Yuan Xie:
Rubik: A Hierarchical Architecture for Efficient Graph Learning. CoRR abs/2009.12495 (2020) - [i27]Jiayi Yang, Lei Deng, Yukuan Yang, Yuan Xie, Guoqi Li:
Training and Inference for Integer-Based Semantic Segmentation Network. CoRR abs/2011.14504 (2020)
2010 – 2019
- 2019
- [j106]Xinfeng Xie
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs. IEEE Comput. Archit. Lett. 18(1): 38-42 (2019) - [j105]Dylan C. Stow
Power Profiling of Modern Die-Stacked Memory. IEEE Comput. Archit. Lett. 18(2): 132-135 (2019) - [j104]Yuan Xie, Jishen Zhao:
Emerging Memory Technologies. IEEE Micro 39(1): 6-7 (2019) - [j103]Itir Akgun, Dylan C. Stow, Yuan Xie:
Network-on-Chip Design Guidelines for Monolithic 3-D Integration. IEEE Micro 39(6): 46-53 (2019) - [j102]Guohao Dai
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 640-653 (2019) - [j101]Ming Cheng
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 834-847 (2019) - [j100]Shuang Wu
L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 30(7): 2043-2051 (2019) - [j99]Shouyi Yin
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. 30(1): 146-160 (2019) - [j98]Liang Chang
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2046-2059 (2019) - [j97]Liang Chang
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2668-2679 (2019) - [c282]Yujie Wu, Lei Deng, Guoqi Li, Jun Zhu, Yuan Xie, Luping Shi:
Direct Training for Spiking Neural Networks: Faster, Larger, Better. AAAI 2019: 1311-1318 - [c281]Jilan Lin
Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator. ASP-DAC 2019: 639-644 - [c280]Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie:
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. ASPLOS 2019: 733-747 - [c279]Gushu Li, Yufei Ding, Yuan Xie:
Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices. ASPLOS 2019: 1001-1014 - [c278]Dylan C. Stow, Itir Akgun
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC 2019: 100 - [c277]Kun Wu
Memory-Bound Proof-of-Work Acceleration for Blockchain Applications. DAC 2019: 177 - [c276]Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, Yuan Xie:
CORN: In-Buffer Computing for Binary Neural Network. DATE 2019: 384-389 - [c275]Alvin Oliver Glova, Itir Akgun
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory. DATE 2019: 800-805 - [c274]Yang Zhao
Memory Trojan Attack on Neural Network Accelerators. DATE 2019: 1415-1420 - [c273]Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie:
NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. EMC2@HPCA/CVPR/ISCA 2019: 11-15 - [c272]Jilan Lin
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators. ACM Great Lakes Symposium on VLSI 2019: 283-286 - [c271]Jiansong Zhang, Lixue Xia, Zhao Jiang, Hao Liang, Jiaoyan Chen, Shouda Liu, Wei Lin, Yuan Xie:
Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices. Hot Chips Symposium 2019: 1-28 - [c270]Abanti Basak, Shuangchen Li, Xing Hu, Sang Min Oh, Xinfeng Xie, Li Zhao, Xiaowei Jiang, Yuan Xie:
Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads. HPCA 2019: 373-386 - [c269]Liu Liu
Dynamic Sparse Graph for Efficient Deep Learning. ICLR (Poster) 2019 - [c268]Mingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. ISLPED 2019: 1-6 - [c267]Maohua Zhu, Tao Zhang, Zhenyu Gu, Yuan Xie:
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs. MICRO 2019: 359-371 - [c266]Pengfei Zuo, Yu Hua, Yuan Xie:
SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads. MICRO 2019: 479-492 - [c265]Wenqin Huangfu, Xueqi Li, Shuangchen Li, Xing Hu, Peng Gu, Yuan Xie:
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm. MICRO 2019: 587-599 - [c264]Mingyu Yan, Xing Hu, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. MICRO 2019: 615-628 - [c263]Dylan C. Stow, Itir Akgun, Yuan Xie:
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. SLIP 2019: 1-8 - [c262]Yuan Xie:
CRISP: Center for Research on Intelligent Storage and Processing-in-Memory. VLSI-DAT 2019: 1 - [i26]Pengfei Zuo, Yu Hua, Yuan Xie:
A Secure and Persistent Memory System for Non-volatile Memory. CoRR abs/1901.00620 (2019) - [i25]Peiqi Wang, Dongsheng Wang, Yu Ji, Xinfeng Xie, Haoxuan Song, XuXin Liu, Yongqiang Lyu, Yuan Xie:
QGAN: Quantized Generative Adversarial Networks. CoRR abs/1901.08263 (2019) - [i24]Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie:
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. CoRR abs/1901.09904 (2019) - [i23]Xing Hu, Ling Liang, Lei Deng, Shuangchen Li, Xinfeng Xie, Yu Ji, Yufei Ding, Chang Liu, Timothy Sherwood, Yuan Xie:
Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints. CoRR abs/1903.03916 (2019) - [i22]Gushu Li, Yufei Ding, Yuan Xie:
SANQ: A Simulation Framework for Architecting Noisy Intermediate-Scale Quantum Computing System. CoRR abs/1904.11590 (2019) - [i21]Yuke Wang, Boyuan Feng, Gushu Li, Lei Deng, Yuan Xie, Yufei Ding:
AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms. CoRR abs/1908.11781 (2019) - [i20]Yukuan Yang, Shuang Wu, Lei Deng, Tianyi Yan, Yuan Xie, Guoqi Li:
Training High-Performance and Large-Scale Deep Neural Networks with Full 8-bit Integers. CoRR abs/1909.02384 (2019) - [i19]Lei Deng, Yujie Wu, Yifan Hu, Ling Liang, Guoqi Li, Xing Hu, Yufei Ding, Peng Li, Yuan Xie:
Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization. CoRR abs/1911.00822 (2019) - [i18]Ao Ren, Tao Zhang, Yuhao Wang, Sheng Lin, Peiyan Dong, Yen-Kuang Chen, Yuan Xie, Yanzhi Wang:
DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks. CoRR abs/1911.08020 (2019) - [i17]Gushu Li, Li Zhou, Nengkun Yu, Yufei Ding, Mingsheng Ying, Yuan Xie:
Poq: Projection-based Runtime Assertions for Debugging on a Quantum Computer. CoRR abs/1911.12855 (2019) - [i16]Gushu Li, Yufei Ding, Yuan Xie:
Towards Efficient Superconducting Quantum Processor Architecture Design. CoRR abs/1911.12879 (2019) - 2018
- [j96]Ling Liang
Crossbar-Aware Neural Network Pruning. IEEE Access 6: 58324-58337 (2018) - [j95]Abanti Basak
Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads. IEEE Comput. Archit. Lett. 17(2): 197-200 (2018) - [j94]Lixue Xia
Stuck-at Fault Tolerance in RRAM Computing Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 102-115 (2018) - [j93]Xing Hu, Dylan C. Stow, Yuan Xie:
Die Stacking Is Happening. IEEE Micro 38(1): 22-28 (2018) - [j92]Kaisheng Ma
IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. IEEE Micro 38(4): 11-19 (2018) - [j91]Lixue Xia
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j90]Yunji Chen
An Instruction Set Architecture for Machine Learning. ACM Trans. Comput. Syst. 36(3): 9:1-9:35 (2018) - [j89]Ing-Chao Lin
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 50-62 (2018) - [j88]Linuo Xue
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 484-495 (2018) - [j87]Maohua Zhu
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 831-840 (2018) - [j86]Mimi Xie
Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2443-2455 (2018) - [c261]Peng Gu, Dylan C. Stow, Prashansa Mukim, Shuangchen Li, Yuan Xie:
Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing. AsianHOST 2018: 74-79 - [c260]Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie:
Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler. ASPLOS 2018: 448-460 - [c259]Kaisheng Ma
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. ASPLOS 2018: 782-796 - [c258]Wenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie:
RADAR: a 3D-reRAM based DNA alignment accelerator architecture. DAC 2018: 59:1-59:6 - [c257]Xianwei Cheng, Yang Zhao
Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs. DAC 2018: 84:1-84:6 - [c256]Peiqi Wang, Yu Ji, Chi Hong, Yongqiang Lyu, Dongsheng Wang, Yuan Xie:
SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory. DAC 2018: 106:1-106:6 - [c255]Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuangang Wang, Yuan Xie:
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory. DATE 2018: 625-628 - [c254]Gushu Li, Guohao Dai, Shuangchen Li, Yu Wang, Yuan Xie:
GraphIA: an in-situ accelerator for large-scale graph processing. MEMSYS 2018: 79-84 - [c253]Xing Hu, Matheus Ogleari, Jishen Zhao, Shuangchen Li, Abanti Basak, Yuan Xie:
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network. MICRO 2018: 494-506 - [c252]Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. MICRO 2018: 696-709 - [c251]Peiqi Wang, Xinfeng Xie, Lei Deng, Guoqi Li, Dongsheng Wang, Yuan Xie:
HitNet: Hybrid Ternary Recurrent Neural Network. NeurIPS 2018: 602-612 - [c250]Yu Ji, Ling Liang, Lei Deng, Youyang Zhang, Youhui Zhang, Yuan Xie:
TETRIS: TilE-matching the TRemendous Irregular Sparsity. NeurIPS 2018: 4119-4129 - [i15]Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie:
Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler. CoRR abs/1801.00746 (2018) - [i14]Liu Liu, Shaoshan Liu, Zhe Zhang, Bo Yu, Jie Tang, Yuan Xie:
PIRT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Applications on Heterogeneous Architectures. CoRR abs/1802.08359 (2018) - [i13]Shuang Wu, Guoqi Li, Lei Deng, Liu Liu, Yuan Xie, Luping Shi:
L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks. CoRR abs/1802.09769 (2018) - [i12]Maohua Zhu, Jason Clemons, Jeff Pool, Minsoo Rhu, Stephen W. Keckler, Yuan Xie:
Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training. CoRR abs/1806.00512 (2018) - [i11]Ling Liang, Lei Deng, Yueling Zeng, Xing Hu, Yu Ji, Xin Ma, Guoqi Li, Yuan Xie:
Crossbar-aware neural network pruning. CoRR abs/1807.10816 (2018) - [i10]Gushu Li, Yufei Ding, Yuan Xie:
Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices. CoRR abs/1809.02573 (2018) - [i9]Xin Ma, Liang Chang, Shuangchen Li, Lei Deng, Yufei Ding, Yuan Xie:
In-memory multiplication engine with SOT-MRAM based stochastic computing. CoRR abs/1809.08358 (2018) - [i8]Liu Liu, Lei Deng, Xing Hu, Maohua Zhu, Guoqi Li, Yufei Ding, Yuan Xie:
Dynamic Sparse Graph for Efficient Deep Learning. CoRR abs/1810.00859 (2018) - [i7]Zhaodong Chen, Lei Deng, Guoqi Li, Jiawei Sun, Xing Hu, Xin Ma, Yuan Xie:
Batch Normalization Sampling. CoRR abs/1810.10962 (2018) - 2017
- [j85]Jishen Zhao, Qiaosha Zou, Yuan Xie:
Overview of 3-D Architecture Design Opportunities and Techniques. IEEE Des. Test 34(4): 60-68 (2017) - [j84]Kaiyuan Guo, Song Han, Song Yao, Yu Wang, Yuan Xie, Huazhong Yang:
Software-Hardware Codesign for Efficient Neural Network Acceleration. IEEE Micro 37(2): 18-25 (2017) - [j83]Chao Wang
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 513-517 (2017) - [j82]Kaisheng Ma
Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems. ACM Trans. Embed. Comput. Syst. 16(4): 107:1-107:23 (2017) - [j81]Qiaosha Zou
Thermomechanical Stress-Aware Management for 3-D IC Designs. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2678-2682 (2017) - [c249]Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie:
POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware. PACT 2017: 148-149 - [c248]Kaisheng Ma
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. ASP-DAC 2017: 678-683 - [c247]Liu Liu
Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC 2017: 751-756 - [c246]Wenqin Huangfu, Lixue Xia
Computation-oriented fault-tolerance schemes for RRAM computing systems. ASP-DAC 2017: 794-799 - [c245]Ming Cheng, Lixue Xia
TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks. DAC 2017: 26:1-26:6 - [c244]Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie:
Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications. DATE 2017: 1245-1248 - [c243]Jaya Dofe, Peng Gu, Dylan C. Stow, Qiaoyan Yu, Eren Kursun, Yuan Xie:
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits. ACM Great Lakes Symposium on VLSI 2017: 321-326 - [c242]Liang Chang
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory. ICCAD 2017: 245-252 - [c241]Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh:
Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD 2017: 728-735 - [c240]Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh:
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA 2017: 678-690 - [c239]Kaisheng Ma
Incidental computing on IoT nonvolatile processors. MICRO 2017: 204-218 - [c238]Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
DRISA: a DRAM-based reconfigurable in-situ accelerator. MICRO 2017: 288-301 - 2016
- [j80]Jishen Zhao, Cong Xu, Tao Zhang, Yuan Xie:
BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories. J. Comput. Sci. Technol. 31(1): 20-35 (2016) - [j79]Kaisheng Ma
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. IEEE Micro 36(3): 72-83 (2016) - [j78]Ping Chi, Wang-Chien Lee, Yuan Xie:
Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1461-1474 (2016) - [j77]Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, Yuan Xie:
TSocket: Thermal Sustainable Power Budgeting. ACM Trans. Design Autom. Electr. Syst. 21(2): 29:1-29:22 (2016) - [j76]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3041-3054 (2016) - [c237]Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie:
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC 2016: 109-114 - [c236]Youhui Zhang, Yu Ji, Wenguang Chen, Yuan Xie:
Neural network transformation under hardware constraints. CASES 2016: 8:1 - [c235]Enes Eken, Linghao Song
NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation. DAC 2016: 70:1-70:6 - [c234]Matthew Poremba, Tao Zhang, Yuan Xie:
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. DAC 2016: 168:1-168:6 - [c233]Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie:
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. DAC 2016: 173:1-173:6 - [c232]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE 2016: 469-474 - [c231]Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI 2016: 347-352 - [c230]Shuangchen Li, Liu Liu
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. ICCAD 2016: 2 - [c229]Dylan C. Stow, Itir Akgun
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration. ICCAD 2016: 56 - [c228]Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie:
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD 2016: 118 - [c227]Itir Akgun
Scalable memory fabric for silicon interposer-based multi-core systems. ICCD 2016: 33-40 - [c226]Peng Gu, Dylan C. Stow, Russell Barnes, Eren Kursun, Yuan Xie:
Thermal-aware 3D design for side-channel information leakage. ICCD 2016: 520-527 - [c225]Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie:
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. ISCA 2016: 27-39 - [c224]Hsiang-Yun Cheng
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA 2016: 103-114 - [c223]Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen
Cambricon: An Instruction Set Architecture for Neural Networks. ISCA 2016: 393-405 - [c222]Lunkai Zhang, Brian Neely, Diana Franklin
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs. ISCA 2016: 519-531 - [c221]Nan Wu
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. ISVLSI 2016: 455-460 - [c220]Dylan C. Stow, Itir Akgun
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space. ISVLSI 2016: 637-642 - [c219]Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen:
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. MICRO 2016: 21:1-21:13 - [c218]Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie:
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO 2016: 28:1-28:13 - [c217]Jia Zhan, Itir Akgun
A unified memory network architecture for in-memory computing in commodity servers. MICRO 2016: 29:1-29:14 - [c216]Zhe Wang, Daniel A. Jiménez
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD 2016: 109-117 - [c215]Mengying Zhao, Keni Qiu, Yuan Xie, Jingtong Hu
Redesigning software and systems for non-volatile processors on self-powered devices. VLSI-SoC 2016: 1-6 - [i6]Nan Wu, Zheyu Liu, Fei Qiao, Xiaojun Guo, Qi Wei, Yuan Xie, Huazhong Yang:
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. CoRR abs/1603.01954 (2016) - [i5]Chao Wang, Qi Yu, Lei Gong, Xi Li, Yuan Xie, Xuehai Zhou:
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. CoRR abs/1605.06894 (2016) - [i4]Maohua Zhu, Liu Liu, Chao Wang, Yuan Xie:
CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis. CoRR abs/1606.06234 (2016) - 2015
- [b1]Yuan Xie, Jishen Zhao:
Die-stacking Architecture. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00619-7 - [j75]Matthew Poremba, Tao Zhang, Yuan Xie:
NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems. IEEE Comput. Archit. Lett. 14(2): 140-143 (2015) - [j74]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. Inf. Media Technol. 10(2): 182-191 (2015) - [j73]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. IPSJ Trans. Syst. LSI Des. Methodol. 8: 2-11 (2015) - [j72]Jue Wang, Yuan Xie:
A Write-Aware STTRAM-Based Register File Architecture for GPGPU. ACM J. Emerg. Technol. Comput. Syst. 12(1): 6:1-6:12 (2015) - [j71]Kaisheng Ma
Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. IEEE Micro 35(5): 32-40 (2015) - [j70]Hsiang-Yun Cheng
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. 12(2): 17:1-17:22 (2015) - [j69]Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin T. Lim, Yuan Xie, Paolo Faraboschi:
Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion. ACM Trans. Archit. Code Optim. 12(3): 31:1-31:24 (2015) - [j68]Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie:
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. 1(4): 195-206 (2015) - [j67]R. Iris Bahar
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. ACM Trans. Design Autom. Electr. Syst. 20(4): 59:1-59:2 (2015) - [j66]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. 20(4): 63:1-63:21 (2015) - [j65]Hsiang-Yun Cheng
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. ACM Trans. Design Autom. Electr. Syst. 21(1): 7:1-7:26 (2015) - [j64]Wulong Liu, Yu Wang
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1842-1853 (2015) - [c214]Yang Zheng, Cong Xu, Yuan Xie:
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues. ASP-DAC 2015: 112-117 - [c213]Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang:
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis. ASP-DAC 2015: 166-171 - [c212]Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie:
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies. ASP-DAC 2015: 785-790 - [c211]Yongpan Liu, Hehe Li, Xueqing Li, Chun Jason Xue, Yuan Xie, Huazhong Yang:
Self-powered wearable sensor node: Challenges and opportunities. CASES 2015: 189 - [c210]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
DimNoC: a dim silicon approach towards power-efficient on-chip network. DAC 2015: 10:1-10:6 - [c209]Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin:
Core vs. uncore: the heart of darkness. DAC 2015: 121:1-121:6 - [c208]Yongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma
Ambient energy harvesting nonvolatile processors: from circuit to system. DAC 2015: 150:1-150:6 - [c207]Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey S. Vetter, Yuan Xie:
DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. DATE 2015: 1543-1546 - [c206]Yu Wang, Tianqi Tang, Lixue Xia
Energy Efficient RRAM Spiking Neural Network for Real Time Classification. ACM Great Lakes Symposium on VLSI 2015: 189-194 - [c205]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - [c204]Kaisheng Ma
Architecture exploration for ambient energy harvesting nonvolatile processors. HPCA 2015: 526-537 - [c203]Kaisheng Ma
Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. ICCAD 2015: 670-675 - [c202]Ke Chen, Sheng Li, Jung Ho Ahn
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - [c201]Shuangchen Li, Ang Li, Yuan Zhe, Yongpan Liu, Peng Li, Guangyu Sun, Yu Wang, Huazhong Yang, Yuan Xie:
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations. ISLPED 2015: 61-66 - [c200]Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan:
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. ISQED 2015: 565-570 - [c199]Kaisheng Ma
Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing. ISVLSI 2015: 339-344 - [c198]Shuangchen Li, Ping Chi, Jishen Zhao, Kwang-Ting Cheng
Leveraging nonvolatility for architecture design with emerging NVM. NVMSA 2015: 1-5 - 2014
- [j63]Wulong Liu, Yu Wang, Xue Feng
Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects. IEEE Des. Test 31(5): 28-35 (2014) - [j62]Jin Liu, Juan Li, Xiaoping Sun, Yuan Xie, Jeff Yu Lei, Qiping Hu:
An Embedded Co-AdaBoost based construction of software document relation coupled resource spaces for cyber-physical society. Future Gener. Comput. Syst. 32: 198-210 (2014) - [j61]Wulong Liu, Yu Wang
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes. ACM J. Emerg. Technol. Comput. Syst. 10(3): 23:1-23:22 (2014) - [j60]Jing Xie, Yang Du, Yuan Xie:
Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology. ACM J. Emerg. Technol. Comput. Syst. 11(1): 5:1-5:17 (2014) - [j59]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. 11(1): 4:1-4:25 (2014) - [j58]Jue Wang, Xiangyu Dong, Yuan Xie:
Preventing STT-RAM Last-Level Caches from Port Obstruction. ACM Trans. Archit. Code Optim. 11(3): 23:1-23:19 (2014) - [j57]Jue Wang, Xiangyu Dong, Yuan Xie:
Building and Optimizing MRAM-Based Commodity Memories. ACM Trans. Archit. Code Optim. 11(4): 36:1-36:22 (2014) - [j56]Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1632-1643 (2014) - [j55]Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1644-1656 (2014) - [j54]Naehyuck Chang, David Z. Pan, Yuan Xie:
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond. ACM Trans. Design Autom. Electr. Syst. 20(1): 1:1-1:2 (2014) - [c197]Qiaosha Zou, Matt Poremba, Yuan Xie:
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests. 3DIC 2014: 1-7 - [c196]Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie:
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 3DIC 2014: 1-7 - [c195]Xing Hu, Yi Xu, Yu Hu, Yuan Xie:
SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network. ASP-DAC 2014: 550-555 - [c194]Jia Zhan, Matthew Poremba, Yi Xu, Yuan Xie:
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. ASP-DAC 2014: 586-591 - [c193]Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie:
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. ASP-DAC 2014: 762-767 - [c192]Cong Xu, Dimin Niu, Shimeng Yu
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC 2014: 825-830 - [c191]Jia Zhan, Yuan Xie, Guangyu Sun:
NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era. DAC 2014: 160:1-160:6 - [c190]Wulong Liu, Guoqing Chen, Xue Han, Yu Wang
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case. DAC 2014: 166:1-166:6 - [c189]Xiaoming Chen, Yu Wang
Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs. DAC 2014: 168:1-168:6 - [c188]Xing Hu, Yi Xu, Jun Ma, Guoqing Chen, Yu Hu, Yuan Xie:
Thermal-Sustainable Power Budgeting for Dynamic Threading. DAC 2014: 187:1-187:6 - [c187]Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie:
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. ACM Great Lakes Symposium on VLSI 2014: 51-56 - [c186]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu
Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI 2014: 145-150 - [c185]Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie:
TSV power supply array electromigration lifetime analysis in 3D ICS. ACM Great Lakes Symposium on VLSI 2014: 239-240 - [c184]Zhe Wang, Daniel A. Jiménez
Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA 2014: 13-24 - [c183]Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie:
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. HPCA 2014: 368-379 - [c182]Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD 2014: 55-62 - [c181]Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie:
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. ICCAD 2014: 301-308 - [c180]Jue Wang, Xiangyu Dong, Yuan Xie:
ProactiveDRAM: A DRAM-initiated retention management scheme. ICCD 2014: 22-27 - [c179]Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie:
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. ISCA 2014: 349-360 - [c178]Ping Chi, Wang-Chien Lee, Yuan Xie:
Making B+-tree efficient in PCM-based main memory. ISLPED 2014: 69-74 - [c177]Hsiang-Yun Cheng
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED 2014: 303-306 - [c176]Jue Wang, Xiangyu Dong, Yuan Xie:
Enabling high-performance LPDDRx-compatible MRAM. ISLPED 2014: 339-344 - [c175]Song Yao, Xiaoming Chen, Yu Wang
Efficient region-aware P/G TSV planning for 3D ICs. ISQED 2014: 171-178 - [c174]Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie:
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. ISQED 2014: 639-644 - [c173]Kaisheng Ma
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed. ISVLSI 2014: 296-301 - [c172]Jishen Zhao, Onur Mutlu, Yuan Xie:
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems. MICRO 2014: 153-165 - [c171]Qiaosha Zou, Yuan Xie:
Compact models and model standard for 2.5D and 3D integration. SLIP 2014: 7:1-7:7 - [e3]Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra:
International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014. ACM 2014, ISBN 978-1-4503-2975-0 [contents] - 2013
- [j53]Xiaoming Chen, Yu Wang
Assessment of Circuit Optimization Techniques Under NBTI. IEEE Des. Test 30(6): 40-49 (2013) - [j52]Xiaoming Chen, Hong Luo, Yu Wang
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. IET Circuits Devices Syst. 7(5): 273-282 (2013) - [j51]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang:
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. 46(1): 1-9 (2013) - [j50]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. 9(1): 5:1-5:20 (2013) - [j49]Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie:
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory. ACM J. Emerg. Technol. Comput. Syst. 9(3): 22:1-22:22 (2013) - [j48]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. 10(4): 23:1-23:22 (2013) - [j47]Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. ACM Trans. Archit. Code Optim. 10(4): 24:1-24:25 (2013) - [j46]Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. 10(4): 51:1-51:21 (2013) - [j45]Yuan Xie, Gabriel H. Loh:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 485-486 (2013) - [j44]Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie:
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1335-1346 (2013) - [c170]Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Designing energy-efficient NoC for real-time embedded systems through slack optimization. DAC 2013: 37:1-37:6 - [c169]Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC 2013: 108:1-108:6 - [c168]Jue Wang, Xiangyu Dong, Yuan Xie:
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. DATE 2013: 847-852 - [c167]Yuan Xie:
Future memory and interconnect technologies. DATE 2013: 964-969 - [c166]Qiaosha Zou, Tao Zhang, Eren Kursun, Yuan Xie:
Thermomechanical stress-aware management for 3D IC designs. DATE 2013: 1255-1258 - [c165]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. HPCA 2013: 234-245 - [c164]Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King:
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. HPCA 2013: 390-399 - [c163]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD 2013: 17-23 - [c162]Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie:
Low power multi-level-cell resistive memory design with incomplete data mapping. ICCD 2013: 131-137 - [c161]Tao Zhang, Cong Xu, Yuan Xie, Guangyu Sun:
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. ICCD 2013: 138-144 - [c160]Peng Wang, Guangyu Sun, Tao Wang, Yuan Xie, Jason Cong:
Designing scratchpad memory architecture with emerging STT-RAM memory technologies. ISCAS 2013: 1244-1247 - [c159]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. ISPASS 2013: 140-141 - [c158]Qiaosha Zou, Jing Xie, Yuan Xie:
Cost-driven 3D design optimization with metal layer reduction technique. ISQED 2013: 294-299 - [c157]Wulong Liu, Haixiao Du, Yu Wang
TSV-aware topology generation for 3D Clock Tree Synthesis. ISQED 2013: 300-307 - [c156]Jing Xie, Yang Du, Yuan Xie:
CPDI: Cross-power-domain interface circuit design in monolithic 3D technology. ISQED 2013: 442-447 - [c155]Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi:
Kiln: closing the performance gap between systems with and without persistence support. MICRO 2013: 421-432 - [e2]Pai H. Chou, Ru Huang, Yuan Xie, Tanay Karnik:
International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013. IEEE 2013, ISBN 978-1-4799-1235-3 [contents] - 2012
- [j43]Yibo Chen, Yu Wang
Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing. J. Electr. Comput. Eng. 2012: 105250:1-105250:14 (2012) - [j42]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
ESL Design Methodology. J. Electr. Comput. Eng. 2012: 358281:1-358281:2 (2012) - [j41]Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi:
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 994-1007 (2012) - [j40]Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Trans. Embed. Comput. Syst. 11(3): 62:1-62:16 (2012) - [j39]Guangyu Sun, Huazhong Yang, Yuan Xie:
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs. ACM Trans. Design Autom. Electr. Syst. 17(2): 13:1-13:20 (2012) - [j38]Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie:
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 186-191 (2012) - [c154]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie:
Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC 2012: 47-52 - [c153]Dimin Niu, Yang Xiao, Yuan Xie:
Low power memristor-based ReRAM design with Error Correcting Code. ASP-DAC 2012: 79-84 - [c152]Jing Xie, Yu Wang, Yuan Xie:
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs. ASP-DAC 2012: 738-743 - [c151]Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das:
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC 2012: 243-252 - [c150]Jue Wang, Xiangyu Dong, Yuan Xie:
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. DAC 2012: 253-258 - [c149]Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. DAC 2012: 1191-1196 - [c148]Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie:
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs. DATE 2012: 1185-1190 - [c147]Guangyu Sun, Cong Xu, Yuan Xie:
Modeling and design exploration of FBDRAM as on-chip memory. DATE 2012: 1507-1512 - [c146]Jing Xie, Vijaykrishnan Narayanan, Yuan Xie:
Mitigating electromigration of power supply networks using bidirectional current stress. ACM Great Lakes Symposium on VLSI 2012: 299-302 - [c145]Jishen Zhao, Yuan Xie:
Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration. ICCAD 2012: 81-87 - [c144]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214 - [c143]Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED 2012: 403-408 - [c142]Hong Luo, Yu Wang
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. ISVLSI 2012: 183-188 - [c141]Matthew Poremba, Yuan Xie:
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories. ISVLSI 2012: 392-397 - [c140]Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC 2012: 33 - [c139]Jin Liu, Juan Li, Yuan Xie, Jeff Yu Lei, Qiping Hu:
An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation. SKG 2012: 173-180 - [r1]Yiran Chen, Hai Li, Yuan Xie, Dimin Niu:
Low-Power Design of Emerging Memory Technologies. Handbook of Energy-Aware and Green Computing 2012: 67-90 - 2011
- [j37]Yuan Xie:
Modeling, Architecture, and Applications for Emerging Memory Technologies. IEEE Des. Test Comput. 28(1): 44-51 (2011) - [j36]Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan:
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 109-119 (2011) - [j35]Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie:
Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Found. Trends Electron. Des. Autom. 5(1-2): 1-151 (2011) - [j34]Yuan Xie, Pol Marchal:
Editorial- three-dimensional integrated circuits design. IET Comput. Digit. Tech. 5(3): 159 (2011) - [j33]Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai (Helen) Li:
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Comput. Digit. Tech. 5(3): 213-220 (2011) - [j32]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. 8(2): 6:1-6:29 (2011) - [j31]Feng Wang, Yibo Chen, Chrysostomos Nicopoulos
Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 295-307 (2011) - [j30]Feng Wang, Yuan Xie:
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model. IEEE Trans. Dependable Secur. Comput. 8(1): 137-146 (2011) - [j29]Yu Wang
Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation. IEEE Trans. Dependable Secur. Comput. 8(5): 756-769 (2011) - [j28]Yu Wang
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 615-628 (2011) - [c138]Xiangyu Dong, Yuan Xie:
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. ASP-DAC 2011: 31-36 - [c137]Wulong Liu, Yu Wang
On-chip hybrid power supply system for wireless sensor nodes. ASP-DAC 2011: 43-48 - [c136]Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie:
A frequent-value based PRAM memory architecture. ASP-DAC 2011: 211-216 - [c135]Jin Ouyang, Yuan Xie:
Enabling quality-of-service in nanophotonic network-on-chip. ASP-DAC 2011: 351-356 - [c134]Qiaosha Zou, Yibo Chen, Yuan Xie, Alan Su:
System-level design space exploration for three-dimensional (3D) SoCs. CODES+ISSS 2011: 385-388 - [c133]Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan:
Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883 - [c132]Jishen Zhao, Xiangyu Dong, Yuan Xie:
An energy-efficient 3D CMP design with fine-grained voltage scaling. DATE 2011: 539-542 - [c131]Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
Design implications of memristor-based RRAM cross-point structures. DATE 2011: 734-739 - [c130]Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta:
Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI 2011: 439-444 - [c129]Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie:
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy. HPCA 2011: 231-242 - [c128]Jishen Zhao, Cong Xu, Yuan Xie:
Bandwidth-aware reconfigurable cache design with hybrid memory technologies. ICCAD 2011: 48-55 - [c127]Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie:
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD 2011: 463-470 - [c126]Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie:
Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD 2011: 175-182 - [c125]Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie:
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. ICCD 2011: 366-372 - [c124]Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu:
F2BFLY: an on-chip free-space optical network with wavelength-switching. ICS 2011: 348-358 - [c123]Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80 - [c122]Guangyu Sun, Christopher J. Hughes
Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA 2011: 377-388 - [c121]Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie:
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs. ISLPED 2011: 397-402 - [c120]Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan:
Impact of Circuit Degradation on FPGA Design Security. ISVLSI 2011: 230-235 - [p1]Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Yuan Xie, Narayanan Vijaykrishnan:
Influence of Stacked 3D Memory/Cache Architectures on GPUs. 3D Integration for NoC-based SoC Architectures 2011: 249-271 - [e1]David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens:
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. ACM 2011, ISBN 978-1-4503-0667-6 [contents] - 2010
- [j27]Gabriel H. Loh, Yuan Xie:
3D Stacked Microprocessor: Are We There Yet? IEEE Micro 30(3): 60-64 (2010) - [j26]Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty
Test-access mechanism optimization for core-based three-dimensional SOCs. Microelectron. J. 41(10): 601-615 (2010) - [j25]Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie:
Design exploration of hybrid caches with disparate memory technologies. ACM Trans. Archit. Code Optim. 7(3): 15:1-15:34 (2010) - [j24]Xiangyu Dong, Jishen Zhao, Yuan Xie:
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1959-1972 (2010) - [j23]Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1621-1624 (2010) - [j22]Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Total Power Optimization for Combinational Logic Using Genetic Algorithms. J. Signal Process. Syst. 58(2): 145-160 (2010) - [c119]Jing Xie, Xiangyu Dong, Yuan Xie:
3D memory stacking for fast checkpointing/restore applications. 3DIC 2010: 1-6 - [c118]Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC 2010: 1-6 - [c117]Jing Xie, Jishen Zhao, Xiangyu Dong, Yuan Xie:
Architectural benefits and design challenges for three-dimensional integrated circuits. APCCAS 2010: 540-543 - [c116]Paul Falkenstern, Yuan Xie, Yao-Wen Chang
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. ASP-DAC 2010: 169-174 - [c115]Dimin Niu
Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC 2010: 193-198 - [c114]Yibo Chen, Yuan Xie, Yu Wang
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment. ASP-DAC 2010: 689-694 - [c113]Yibo Chen, Yuan Xie, Yu Wang
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library. ASP-DAC 2010: 781-786 - [c112]Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC 2010: 1-4 - [c111]Jishen Zhao, Xiangyu Dong, Yuan Xie:
Cost-aware three-dimensional (3D) many-core multiprocessor design. DAC 2010: 126-131 - [c110]Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das
Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155 - [c109]Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie:
Impact of process variations on emerging memristor. DAC 2010: 877-882 - [c108]Yongsoo Joo, Dimin Niu
Energy- and endurance-aware design of phase change memory caches. DATE 2010: 136-141 - [c107]Guangyu Sun, Yongsoo Joo
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA 2010: 1-12 - [c106]Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. ICCAD 2010: 471-476 - [c105]Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie:
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD 2010: 477-482 - [c104]Dimin Niu, Yiran Chen, Yuan Xie:
Low-power dual-element memristor based memory design. ISLPED 2010: 25-30 - [c103]Yibo Chen, Jishen Zhao, Yuan Xie:
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. ISLPED 2010: 55-60 - [c102]Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu
Modeling TSV open defects in 3D-stacked DRAM. ITC 2010: 174-182 - [c101]Jin Ouyang, Yuan Xie:
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. MICRO 2010: 409-420 - [c100]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11 - [c99]Yuan Xie:
Processor Architecture Design Using 3D Integration Technology. VLSI Design 2010: 446-451
2000 – 2009
- 2009
- [j21]Yuan Xie, Yibo Chen:
Statistical High-Level Synthesis under Process Variability. IEEE Des. Test Comput. 26(4): 78-87 (2009) - [j20]David S. Kung, Yuan Xie:
Guest Editors' Introduction: Opportunities and Challenges of 3D Integration. IEEE Des. Test Comput. 26(5): 4-5 (2009) - [j19]Hong Luo, Yu Wang
Temperature-Aware NBTI Modeling Techniques in Digital Circuits. IEICE Trans. Electron. 92-C(6): 875-886 (2009) - [j18]Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang
New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. Int. J. Parallel Program. 37(4): 417-431 (2009) - [j17]Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty
Scan-chain design and optimization for three-dimensional integrated circuits. ACM J. Emerg. Technol. Comput. Syst. 5(2): 9:1-9:26 (2009) - [j16]Madhu Mutyam
Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009) - [j15]Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu:
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Secur. Comput. 6(3): 202-216 (2009) - [c98]Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith:
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC 2009: 1-5 - [c97]Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin:
Arithmetic unit design using 180nm TSV-based 3D stacking technology. 3DIC 2009: 1-4 - [c96]Yaoyao Ye, Lian Duan, Jiang Xu
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC 2009: 1-6 - [c95]Yibo Chen, Yuan Xie:
Tolerating process variations in high-level synthesis using transparent latches. ASP-DAC 2009: 73-78 - [c94]Feng Wang, Yuan Xie, Andrés Takach:
Variation-aware resource sharing and binding in behavioral synthesis. ASP-DAC 2009: 79-84 - [c93]Xiangyu Dong, Yuan Xie:
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). ASP-DAC 2009: 234-241 - [c92]Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang
A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC 2009: 455-460 - [c91]Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan:
A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC 2009: 763-768 - [c90]Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES 2009: 175-184 - [c89]Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Gate replacement techniques for simultaneous leakage and aging optimization. DATE 2009: 328-333 - [c88]Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie:
Power and performance of read-write aware Hybrid Caches with non-volatile memories. DATE 2009: 737-742 - [c87]Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen:
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249 - [c86]Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie:
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. ICCAD 2009: 164-171 - [c85]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD 2009: 269-275 - [c84]Brandon Noia, Krishnendu Chakrabarty
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. ICCD 2009: 70-77 - [c83]Ahmed Al-Maashri
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. ICCD 2009: 254-259 - [c82]Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie:
Hybrid cache architecture with disparate memory technologies. ISCA 2009: 34-45 - [c81]Guangyu Sun, Xiaoxia Wu, Yuan Xie:
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. ISLPED 2009: 295-298 - [c80]Norman P. Jouppi, Yuan Xie:
Emerging technologies and their impact on system design. ISLPED 2009: 427-428 - [c79]Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang
NBTI-aware statistical circuit delay assessment. ISQED 2009: 13-18 - [c78]Yu Wang
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED 2009: 19-26 - [c77]Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin:
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. NANOARCH 2009: 51-56 - [c76]Luca P. Carloni, Partha Pande, Yuan Xie:
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. NOCS 2009: 93-102 - [c75]Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie:
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009 - 2008
- [j14]Yuan Xie, Jason Cong, Paul D. Franzon
Editorial: Special issue on 3D integrated circuits and microarchitectures. ACM J. Emerg. Technol. Comput. Syst. 4(4): 15:1-15:2 (2008) - [j13]Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari:
Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Secur. Comput. 5(2): 115-127 (2008) - [j12]Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Design Space Exploration for 3-D Cache. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 444-455 (2008) - [j11]Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie:
Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 861-873 (2008) - [c74]Feng Wang, Xiaoxia Wu, Yuan Xie:
Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC 2008: 2-9 - [c73]Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen:
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559 - [c72]Feng Wang, Guangyu Sun, Yuan Xie:
A Variation Aware High Level Synthesis Framework. DATE 2008: 1063-1068 - [c71]Syed M. Alam, Mike Ignatowski, Yuan Xie:
Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI 2008: 1-2 - [c70]Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim:
A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 - [c69]Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan:
Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727 - [c68]Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie:
Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205 - [c67]Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty
Test-access mechanism optimization for core-based three-dimensional SOCs. ICCD 2008: 212-218 - [c66]Feng Wang, Yuan Xie:
Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. IPDPS 2008: 1-5 - [c65]Dongkook Park, Soumya Eachempati, Reetuparna Das
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 - [c64]Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu:
Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683 - [c63]Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty
Test-Access Solutions for Three-Dimensional SOCs. ITC 2008: 1 - [c62]Hai Lin, Guangyu Sun, Yunsi Fei
Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. SASP 2008: 63-68 - [c61]Xuebin Wu, Zhiyuan Yan, Yuan Xie:
Two-dimensional crosstalk avoidance codes. SiPS 2008: 106-111 - [c60]Yibo Chen, Jin Ouyang, Yuan Xie:
ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30 - [c59]Jin Ouyang, Yuan Xie:
Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214 - 2007
- [j10]Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
On-chip bus thermal analysis and optimisation. IET Comput. Digit. Tech. 1(5): 590-599 (2007) - [j9]Gabriel H. Loh, Yuan Xie, Bryan Black:
Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007) - [j8]Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Code Decompression Unit Design for VLIW Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 975-980 (2007) - [j7]Chang Hong Lin, Yuan Xie, Wayne H. Wolf:
Code Compression for VLIW Embedded Systems Using a Self-Generating Table. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1160-1171 (2007) - [j6]Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Reliability-aware Co-synthesis for Embedded Systems. J. VLSI Signal Process. 49(1): 87-99 (2007) - [c58]Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. DATE 2007: 546-551 - [c57]Feng Wang, Yuan Xie, Hai Ju:
A novel criticality computation method in statistical timing analysis. DATE 2007: 1611-1616 - [c56]Feng Wang, Chrysostomos Nicopoulos
Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603 - [c55]Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan:
FPGA routing architecture analysis under variations. ICCD 2007: 152-157 - [c54]Xiaoxia Wu, Paul Falkenstern, Yuan Xie:
Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD 2007: 208-214 - [c53]Jongman Kim, Chrysostomos Nicopoulos
A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149 - [c52]Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
Modeling of PMOS NBTI Effect Considering Temperature Variation. ISQED 2007: 139-144 - [c51]Amol Mupid, Madhu Mutyam
Variation Analysis of CAM Cells. ISQED 2007: 333-338 - [c50]Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916 - [c49]Alex K. Jones
Collaborative VLSI-CAD Instruction in the Digital Sandbox. MSE 2007: 141-142 - [c48]Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. PATMOS 2007: 160-170 - [c47]Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108 - [c46]Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan:
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design 2007: 165-170 - [i3]Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Thermal-Aware Task Allocation and Scheduling for Embedded Systems. CoRR abs/0710.4660 (2007) - [i2]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. CoRR abs/0710.4684 (2007) - [i1]Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. CoRR abs/0710.4731 (2007) - 2006
- [j5]Narayanan Vijaykrishnan, Yuan Xie:
Reliability Concerns in Embedded System Designs. Computer 39(1): 118-120 (2006) - [j4]Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein:
Design space exploration for 3D architectures. ACM J. Emerg. Technol. Comput. Syst. 2(2): 65-103 (2006) - [j3]Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 525-536 (2006) - [j2]Yuan Xie, Wei-Lun Hung:
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. J. VLSI Signal Process. 45(3): 177-189 (2006) - [c45]Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo:
Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963 - [c44]Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie:
Optimal topology exploration for application-specific 3D architectures. ASP-DAC 2006: 390-395 - [c43]Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari:
FLAW: FPGA lifetime awareness. DAC 2006: 630-635 - [c42]Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
On-chip bus thermal analysis and optimization. DATE 2006: 850-855 - [c41]Wei-Lun Hung, Xiaoxia Wu, Yuan Xie:
Guaranteeing performance yield in high-level synthesis. ICCAD 2006: 303-309 - [c40]Feihui Li, Chrysostomos Nicopoulos
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141 - [c39]Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104 - [c38]Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie:
Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348 - [c37]Madhu Mutyam
Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360 - [c36]Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo:
Dependability Analysis of Nano-scale FinFET circuits. ISVLSI 2006: 399-404 - [c35]Xiaoxia Wu, Feng Wang, Yuan Xie:
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design. SoCC 2006: 91-92 - [c34]Balaji Vaidyanathan, Yuan Xie:
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. SoCC 2006: 193-196 - [c33]Qian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie:
Modeling the Impact of Process Variation on Critical Charge Distribution. SoCC 2006: 243-246 - [c32]R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502 - [c31]Thomas D. Richardson, Chrysostomos Nicopoulos
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664 - 2005
- [c30]Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1 - [c29]Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie:
Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544 - [c28]John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link:
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC 2005: 709-712 - [c27]Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69 - [c26]Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231 - [c25]Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899 - [c24]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263 - [c23]Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524 - [c22]Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie:
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. ICCD 2005: 677-682 - [c21]Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner:
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696 - [c20]Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369 - [c19]Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung:
Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380 - [c18]Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye
Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639 - [c17]Daniel Hostetler, Yuan Xie:
Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. ISVLSI 2005: 186-191 - [c16]Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang:
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170 - [c15]Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379 - 2004
- [c14]Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50 - [c13]Chang Hong Lin, Yuan Xie, Wayne H. Wolf:
LZW-Based Code Compression for VLIW Embedded Systems. DATE 2004: 76-81 - [c12]Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303 - [c11]Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin:
Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110 - [c10]Wei-Lun Hung, Charles Addo-Quaye
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437 - [c9]Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508 - 2003
- [j1]Yuan Xie, Jiang Xu, Wayne H. Wolf:
Augmenting Platform-Based Design with Synthesis Tools. J. Circuits Syst. Comput. 12(2): 125-142 (2003) - [c8]Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Profile-Driven Selective Code Compression. DATE 2003: 10462-10467 - [c7]Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. DCC 2003: 382-391 - [c6]Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Effect of Power Optimizations on Soft Error Rate. VLSI-SoC (Selected Papers) 2003: 1-20 - 2002
- [c5]Haris Lekatsas, Wayne H. Wolf, Yuan Xie:
Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ISSS 2002: 138-143 - 2001
- [c4]Yuan Xie, Wayne H. Wolf:
Allocation and scheduling of conditional task graph in hardware/software co-synthesis. DATE 2001: 620-625 - [c3]Yuan Xie, Haris Lekatsas, Wayne H. Wolf:
Code Compression for VLIW Processors. Data Compression Conference 2001: 525 - [c2]Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
A code decompression architecture for VLIW processors. MICRO 2001: 66-75 - 2000
- [c1]Yuan Xie, Wayne H. Wolf:
Co-synthesis with custom ASICs. ASP-DAC 2000: 129-134
Coauthor Index
[j153] [j152] [i76] [j143] [j141] [j138] [j137] [j136] [j135] [j134] [c341] [c335] [c329] [c317] [i73] [i67] [j133] [j130] [j129] [j126] [j125] [j121] [j120] [c315] [c312] [c305] [i49] [j119] [j116] [j115] [j114] [j113] [j111] [j110] [j107] [c300] [c293] [c290] [c289] [c283] [i39] [i38] [i37] [i35] [i32] [i30] [i28] [i27] [j100] [c282] [c274] [c272] [c269] [c268] [c264] [i23] [i21] [i20] [i19] [j96] [c251] [c250] [i13] [i11] [i9] [i8] [i7]
[c357] [j163] [j162] [j159] [j158] [j153] [j152] [c351] [c348] [c346] [c345] [j147] [j139] [j138] [j136] [j135] [c343] [c342] [c338] [c336] [c328] [c326] [c323] [c321] [c319] [c318] [c316] [i72] [i70] [i69] [i58] [i57] [j121] [c315] [c309] [c308] [c307] [c306] [c305] [c304] [c303] [c302] [i52] [i50] [i47] [i46] [i45] [i44] [i43] [i42] [j116] [j115] [j112] [c300] [c299] [c298] [c289] [c287] [c283] [i38] [i30] [i28] [j98] [c279] [c269] [i23] [i22] [i21] [i19] [i17] [i16] [i10] [i9] [i8]
[j153] [j152] [j138] [j136] [c317] [i67] [j126] [j125] [j123] [j122] [j121] [c314] [c312] [j116] [j115] [j109] [j107] [c300] [c293] [c283] [i38] [i37] [i29] [i28] [j106] [c280] [c277] [c275] [c274] [c273] [c272] [c270] [c269] [c268] [c265] [c264] [i24] [i23] [i19] [j96] [j95] [j93] [c258] [c253] [c252] [i11] [i8] [i7] [j77] [c195] [c188]
Mahmut T. Kandemir
aka: Mahmut Taylan Kandemir
aka: Mahmut Taylan Kandemir
[j161] [c349] [c347] [j150] [j145] [j141] [c325] [c324] [j124] [c309] [c305] [j116] [j109] [c300] [c292] [c291] [c290] [c289] [c283] [i30] [j106] [j99] [c280] [c277] [c275] [c274] [c273] [c272] [c270] [c268] [c265] [c264] [i24] [i23] [j95] [j86] [c261] [c258] [c255] [c254] [c253] [c252] [i9] [c247] [c238] [j79] [c237] [c233] [c231] [c230] [c225] [c219] [j71] [c213] [c208] [c204] [c201] [c198]
Matthew Poremba
aka: Matt Poremba
aka: Matt Poremba
Narayanan Vijaykrishnan
aka: Vijaykrishnan Narayanan
aka: Vijaykrishnan Narayanan
[j92] [c259] [j82] [c248] [c239] [j79] [j71] [c204] [c203] [c200] [c199] [j56] [c173] [j50] [c170] [c164] [j40] [c151] [c146] [j36] [j31] [c133] [c130] [c123] [c120] [p1] [j22] [j18] [j16] [j15] [c92] [c91] [c77] [j13] [j12] [j11] [c70] [c69] [c68] [c65] [c64] [j10] [j6] [c56] [c55] [c53] [c51] [c50] [c47] [i3] [i1] [j5] [c45] [c43] [c42] [c40] [c39] [c38] [c37] [c32] [c31] [c30] [c29] [c27] [c26] [c25] [c23] [c21] [c18] [c16] [c15] [c14] [c12] [c11] [c10] [c9] [c6]
[j155] [c349] [c341] [c338] [c327] [c318] [i72] [j123] [i50] [i47] [c295] [j102] [j101] [c281] [c277] [j94] [j91] [c254] [j84] [c246] [c245] [c232] [c225] [j64] [c206] [c201] [j63] [j61] [j55] [c190] [c189] [c175] [j53] [j52] [c157] [j43] [c154] [c152] [c149] [c142] [j29] [j28] [c137] [c116] [c114] [c113] [j19] [j18] [c92] [c89] [c79] [c78] [c58] [c52] [c48]
Marilyn Wolf
aka: Wayne H. Wolf
aka: Wayne H. Wolf
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