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Xu Cheng 0001
Person information
- affiliation: Peking University, Microprocessor Research and Development Center, Beijing, China
Other persons with the same name
- Xu Cheng — disambiguation page
- Xu Cheng 0002
— Fudan University, State Key Laboratory of ASIC and System, Shanghai, China (and 2 more)
- Xu Cheng 0003
- Xu Cheng 0004 — Simon Fraser University, Burnaby, BC, Canada
- Xu Cheng 0005
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2020 – today
- 2024
- [c62]Wenjing Cai, Ziyuan Zhu, Yuxin Liu, Yusha Zhang, Xu Cheng:
Oblivious Demand Paging with Ring ORAM in RISC-V Trusted Execution Environments. CSCWD 2024: 1740-1745 - 2023
- [j9]Hongwei Cui, Chun Yang, Xu Cheng:
Secure Speculation via Speculative Secret Flow Tracking. J. Comput. Sci. Technol. 38(2): 422-438 (2023) - [j8]Dongwei Chen
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. ACM Trans. Archit. Code Optim. 20(2): 30:1-30:24 (2023) - [j7]Yujie Cui
Information Leakage Attacks Exploiting Cache Replacement in Commercial Processors. IEEE Trans. Computers 72(9): 2536-2547 (2023) - [j6]Guang Wang
A High-Coverage and Efficient Instruction-Level Testing Approach for x86 Processors. IEEE Trans. Computers 72(11): 3203-3217 (2023) - [c61]Hongwei Cui, Yujie Cui
MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies. PACT 2023: 297-308 - [c60]Wenjing Cai, Ziyuan Zhu, Yuxin Liu, Yusha Zhang, Xu Cheng:
Detecting and Mitigating Cache Side Channel Threats on Intel SGX. CSCWD 2023: 972-977 - [c59]Hongwei Cui, Shuhao Liang, Yujie Cui
A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation. DATE 2023: 1-2 - [c58]Honglan Zhan
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. DATE 2023: 1-6 - 2022
- [c57]Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, Xu Cheng:
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. PACT 2022: 532-533 - [c56]Yujie Cui
Abusing Cache Line Dirty States to Leak Information in Commercial Processors. HPCA 2022: 82-97 - [c55]Guang Wang, Ziyuan Zhu, Xu Cheng, Dan Meng:
In-depth Testing of x86 Instruction Disassemblers with Feedback Controlled DFS Algorithm. ICCD 2022: 463-470 - 2021
- [c54]Guang Wang, Ziyuan Zhu, Shuan Li, Xu Cheng, Dan Meng:
Differential Testing of x86 Instruction Decoders with Instruction Operand Inferring Algorithm. ICCD 2021: 196-203 - [c53]Dongwei Chen
MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety. ICCD 2021: 208-211 - [i5]Yujie Cui, Xu Cheng:
Abusing Cache Line Dirty States to Leak Information in Commercial Processors. CoRR abs/2104.08559 (2021) - 2020
- [i4]Dongwei Chen, Daliang Xu, Dong Tong, Kang Sun, Xuetao Guan, Chun Yang, Xu Cheng:
SMA: Eliminate Memory Spatial Errors via Saturation Memory Access. CoRR abs/2002.02831 (2020) - [i3]Daliang Xu, Dongwei Chen, Chun Yang, Kang Sun, Xu Cheng, Dong Tong:
DangKiller: Eliminating Dangling Pointers Efficiently via Implicit Identifier. CoRR abs/2003.00175 (2020) - [i2]Kang Sun, Daliang Xu, Dongwei Chen, Xu Cheng, Dong Tong:
S3Library: Automatically Eliminating C/C++ Buffer Overflow using Compatible Safer Libraries. CoRR abs/2004.09062 (2020)
2010 – 2019
- 2019
- [i1]Yikun Ban, Yuchen Zhou, Jingrui He, Xu Cheng, Jiangfang Yi:
Coalesced TLB to Exploit Diverse Contiguity of Memory Mapping. CoRR abs/1908.08774 (2019) - 2017
- [c52]Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng:
A Staged Memory Resource Management Method for CMP systems. ASAP 2017: 91-98 - [c51]Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng:
Locality-aware bank partitioning for shared DRAM MPSoCs. ASP-DAC 2017: 770-775 - [c50]Yan Sui, Chun Yang, Xu Cheng:
Understanding the I/O Behavior of Desktop Applications in Virtualization. Conf. Computing Frontiers 2017: 156-163 - [c49]Mingzhu Zhang, Yan Chen, Ruoxi Liu, Xu Cheng, Yi Jiao, Jiakui Zhao, Ouyang Hong:
Prediction of distribution network malfunction based on meteorological factors. ICNC-FSKD 2017: 1028-1032 - [c48]Chun Yang, Xianhua Liu
Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching. VEE 2017: 214-227 - 2016
- [c47]Yan Sui, Chun Yang, Ning Jia, Xu Cheng:
vSIP: virtual scheduler for interactive performance. Conf. Computing Frontiers 2016: 222-231 - [c46]Yan Sui, Chun Yang, Dong Tong, Xianhua Liu
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. ICCD 2016: 576-583 - 2015
- [c45]Mingkai Huang, Xianhua Liu
Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores. ICA3PP (4) 2015: 293-307 - [c44]Mingkai Huang, Dan He, Xianhua Liu
An Energy-Efficient Branch Prediction with Grouped Global History. ICPP 2015: 140-149 - 2014
- [j5]Lingda Li, Junlin Lu, Xu Cheng:
Retention Benefit Based Intelligent Cache Replacement. J. Comput. Sci. Technol. 29(6): 947-961 (2014) - [c43]Ning Jia
DTT: program structure-aware indirect branch optimization via direct-TPC-table in DBT system. Conf. Computing Frontiers 2014: 12:1-12:10 - [c42]Mingli Xie, Dong Tong, Kan Huang, Xu Cheng:
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning. HPCA 2014: 344-355 - [c41]Lingda Li
Block value based insertion policy for high performance last-level caches. ICS 2014: 63-72 - [c40]Ning Jia
SPTU: Improving Dynamic Binary Translation through Software Prediction with Target Updating. SYSTOR 2014: 2:1-2:12 - 2013
- [c39]Zichao Xie, Dong Tong, Xu Cheng:
An energy-efficient branch prediction technique via global-history noise reduction. ISLPED 2013: 211-216 - [c38]Mingli Xie, Dong Tong, Yi Feng, Kan Huang, Xu Cheng:
Page policy control with memory partitioning for DRAM performance and power efficiency. ISLPED 2013: 298-303 - 2012
- [j4]Zichao Xie, Dong Tong, Mingkai Huang, Qinqing Shi, Xu Cheng:
SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers. J. Comput. Sci. Technol. 27(4): 754-768 (2012) - [c37]Lingda Li
Optimal bypass monitor for high performance last-level caches. PACT 2012: 315-324 - [c36]Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong:
An integrated and automated memory optimization flow for FPGA behavioral synthesis. ASP-DAC 2012: 257-262 - [c35]Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng:
Energy-efficient branch prediction with Compiler-guided History Stack. DATE 2012: 449-454 - [c34]Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng:
Improving inclusive cache performance with two-level eviction priority. ICCD 2012: 387-392 - [c33]Mingxing Tan, Xianhua Liu
CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern. ICS 2012: 111-120 - [c32]Qi Zhong, Xuetao Guan, Tao Huang, Xu Cheng, Keyi Wang:
Affinity-aware DMA buffer management for reducing off-chip memory access. SAC 2012: 1588-1593 - [c31]Tao Huang, Qi Zhong, Xuetao Guan, Xiaoyin Wang, Xu Cheng, Keyi Wang:
Reducing last level cache pollution through OS-level software-controlled region-based partitioning. SAC 2012: 1779-1784 - 2011
- [c30]Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng:
TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers. ICCD 2011: 119-126 - [c29]Yan Niu, Chun Yang, Xu Cheng:
Dynamic Memory Demand Estimating Based on the Guest Operating System Behaviors for Virtual Machines. ISPA 2011: 81-86 - 2010
- [j3]Xu Cheng, Xiaoyin Wang, Junlin Lu, Jiangfang Yi, Dong Tong, Xuetao Guan, Feng Liu, Xianhua Liu, Chun Yang, Yi Feng:
Research Progress of UniCore CPUs and PKUnity SoCs. J. Comput. Sci. Technol. 25(2): 200-213 (2010) - [c28]Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A 3D SoC design for H.264 application with on-chip DRAM stacking. 3DIC 2010: 1-6 - [c27]Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A customized design of DRAM controller for on-chip 3D DRAM stacking. CICC 2010: 1-4 - [c26]Hao Li, Dong Tong, Kan Huang, Xu Cheng:
FEMU: a firmware-based emulation framework for SoC verification. CODES+ISSS 2010: 257-266 - [c25]Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng:
FPGA prototyping of an amba-based windows-compatible SoC. FPGA 2010: 13-22 - [c24]Jiyu Zhang, Zhiru Zhang
Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA 2010: 59-68 - [c23]Shu Liu, Xu Cheng, Xuetao Guan, Dong Tong:
Energy efficient management scheme for heterogeneous secondary storage system in mobile computers. SAC 2010: 251-257 - [c22]Dan Liu, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang:
TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures. SoCC 2010: 182-187
2000 – 2009
- 2009
- [c21]Yansong Zheng, Dong Tong, Hao Li, Keyi Wang, Xu Cheng:
Track Down HW Function Faults Using Real SW Invariants. CSIE (3) 2009: 248-253 - [c20]Zichao Xie, Dong Tong, Xu Cheng:
WHOLE: A low energy I-Cache with separate way history. ICCD 2009: 137-143 - [c19]Yang Zhang, Xuetao Guan, Tao Huang, Xu Cheng:
A Heterogeneous Auto-offloading Framework Based on Web Browser for Resource-Constrained Devices. ICIW 2009: 193-199 - [c18]Yubin Xia, Chun Yang, Xu Cheng:
PaS: A Preemption-aware Scheduling Interface for Improving Interactive Performance in Consolidated Virtual Machine Environment. ICPADS 2009: 340-347 - 2008
- [j2]Han-Xin Sun, Kun-Peng Yang, Yulai Zhao, Dong Tong, Xu Cheng:
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. J. Comput. Sci. Technol. 23(1): 141-153 (2008) - [c17]Xu Cheng:
Super-K: A SoC for single-chip ultra mobile computer. ASP-DAC 2008: 284 - [c16]Yubin Xia, Yan Niu, Yansong Zheng, Ning Jia, Chun Yang, Xu Cheng:
Analysis and Enhancement for Interactive-Oriented Virtual Machine Scheduling. EUC (2) 2008: 393-398 - 2007
- [j1]Yulai Zhao, Xianfeng Li, Dong Tong, Xu Cheng:
An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. J. Comput. Sci. Technol. 22(1): 15-24 (2007) - [c15]Jiu-Tao Nie, Xu Cheng:
An Efficient SSA-Based Algorithm for Complete Global Value Numbering. APLAS 2007: 319-334 - [c14]Ning Qu, Yansong Zheng, Wei Cao, Xu Cheng:
GISP: A Transparent Superpage Support Framework for Linux. ASAP 2007: 359-364 - [c13]Xianfeng Li, Abhik Roychoudhury
A Retargetable Software Timing Analyzer Using Architecture Description Language. ASP-DAC 2007: 396-401 - [c12]Yi Feng, Zheng Zhou, Dong Tong, Xu Cheng:
Clock domain crossing fault model and coverage metric for validation of SoC design. DATE 2007: 1385-1390 - [c11]Chun Yang, Yan Niu, Yubin Xia, Xu Cheng:
A Fast Lossless Codec of Continuous-Tone Images for Thin Client Computing. DCC 2007: 409 - [c10]Yulai Zhao, Xianfeng Li, Dong Tong, Xu Cheng:
Reuse Distance Based Cache Leakage Control. HiPC 2007: 356-367 - [c9]Xianhua Liu, Jiyu Zhang, Xu Cheng:
NISD: A Framework for Automatic Narrow Instruction Set Design. ICESS 2007: 271-282 - [c8]Xianhua Liu
Efficient code size reduction without performance loss. SAC 2007: 666-672 - [c7]Ning Qu, Yulai Zhao, Xuetao Guan, Xu Cheng:
Unichos: a full system simulator for thin client platform. SAC 2007: 1552-1556 - [c6]Chun Yang, Yan Niu, Yubin Xia, Xu Cheng:
A Fast and Efficient Codec for Multimedia Applications in Wireless Thin-Client Computing. WOWMOM 2007: 1-12 - 2006
- [c5]Shu Shi, Feng Liu, Xu Cheng:
A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability. ESTIMedia 2006: 13-18 - 2005
- [c4]Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang
Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861 - [c3]Yuanrui Zhang, Shu Liu, Weijia Jia, Xu Cheng:
BluePower - A New Distributed Multihop Scatternet Formation Protocol for Bluetooth Networks. ICPP 2005: 287-294 - [c2]Qiang Liu, Dong Tong, Xu Cheng:
Non-interleaving architecture for hardware implementation of modular multiplication. ISCAS (1) 2005: 660-663 - [c1]Junjuan Xu, Jason Cong, Xu Cheng:
Lower-bound estimation for multi-bitwidth scheduling. ISCAS (1) 2005: 696-699
Coauthor Index
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last updated on 2024-12-23 20:31 CET by the dblp team
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