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Xu Cheng 0002
Person information
- affiliation: Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
- affiliation (2007 - 2009): Cypress Semiconductor Corporation, Ireland Design Centre, Ireland
- affiliation (PhD 2007): University College Cork, Tyndall National Institute, Ireland
Other persons with the same name
- Xu Cheng — disambiguation page
- Xu Cheng 0001
— Peking University, Microprocessor Research and Development Center, Beijing, China
- Xu Cheng 0003
- Xu Cheng 0004 — Simon Fraser University, Burnaby, BC, Canada
- Xu Cheng 0005
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2020 – today
- 2024
- [j26]Zhen Li
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits 59(7): 2248-2259 (2024) - [j25]Yongliang Zhang, Yitong Rong
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 320-333 (2024) - [j24]Yuanyuan Han
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1416-1420 (2024) - [j23]Jiawei Wang, Zhao Gao, Xu Cheng
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024) - 2023
- [j22]Song Wang
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. Microelectron. J. 136: 105778 (2023) - [j21]Yan Liu
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1639-1648 (2023) - [j20]Yan Li
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4015-4027 (2023) - [j19]Baijie Zhang
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5242-5253 (2023) - [c20]Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han:
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC 2023: 1-2 - 2022
- [c19]Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng:
An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. APCCAS 2022: 481-484 - [c18]Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS 2022: 848-851 - [c17]Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS 2022: 2768-2772 - [c16]Min Li, Jue Wang, Xu Cheng, Xiaoyang Zeng:
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. ISCAS 2022: 2876-2880 - [c15]Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS 2022: 2933-2937 - 2021
- [j18]Jue Wang
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110: 105007 (2021) - [j17]Weizhen Wang
An energy-efficient crypto-extension design for RISC-V. Microelectron. J. 115: 105165 (2021) - [j16]Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng:
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. 116: 105219 (2021) - [j15]Yuanyuan Han
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2962-2975 (2021) - [j14]Chiyu Tan
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 3044-3057 (2021) - [c14]Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiaoyang Zeng:
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. ASICON 2021: 1-4 - [c13]Hui Zhang, Zhaojie Li, Heqing Yang, Xu Cheng, Xiaoyang Zeng:
A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network. ASICON 2021: 1-4 - [c12]Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC 2021: 1-3 - 2020
- [j13]Guozhu Xin
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2672-2684 (2020) - [j12]Yan Li
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1619-1623 (2020) - [j11]Yuanyuan Han
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1089-1093 (2020) - [c11]Yan Li
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC 2020: 1-6 - [c10]Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng:
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS 2020: 1-5 - [c9]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j10]Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng:
A 24-bit sigma-delta ADC with configurable chopping scheme. IEICE Electron. Express 16(10): 20190176 (2019) - 2016
- [j9]Xu Cheng, Xiaoyang Zeng, Qi Feng:
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. Microelectron. J. 58: 23-31 (2016) - [j8]Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng:
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 346-350 (2016) - [j7]Liang Wen, Xu Cheng, Keji Zhou
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 643-647 (2016) - 2015
- [j6]Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng:
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12(4): 20150001 (2015) - [j5]Xiaoyang Zeng, Yi Li, Yuejun Zhang
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - 2014
- [j4]Yi Li, Liang Wen, Yuejun Zhang
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014) - [j3]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014) - 2013
- [j2]Yue Wu, Xu Cheng, Xiaoyang Zeng:
A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. Microelectron. J. 44(12): 1260-1267 (2013) - [c8]Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng:
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON 2013: 1-4 - [c7]Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng:
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. ASICON 2013: 1-4 - [c6]Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng:
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS 2013: 154-157 - [c5]Yue Wu, Xu Cheng, Xiaoyang Zeng:
A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. ISCAS 2013: 2014-2017 - 2012
- [j1]Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9(16): 1355-1361 (2012) - 2011
- [c4]Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng:
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. ASICON 2011: 465-468 - [c3]Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng:
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. ASICON 2011: 484-487 - [c2]Li Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng:
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. ASICON 2011: 504-507 - [c1]Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A low power 1.0 GHz VCO in 65nm-CMOS LP-process. ASICON 2011: 1006-1009
Coauthor Index
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last updated on 2024-12-23 20:31 CET by the dblp team
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