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Xiaoyong Xue
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2020 – today
- 2024
- [j24]Chenyang Zhao
, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. IEEE J. Solid State Circuits 59(10): 3277-3289 (2024) - [j23]Yuanyuan Han
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1416-1420 (2024) - [c39]Lizhou Wu, Chenyang Zhao
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC 2024: 551-556 - [c38]Xiaoyong Xue
Optimal Solution Guided Branching Strategy for Neural Network Branch and Bound Verification. ICECCS 2024: 67-87 - 2023
- [j22]Jingwen Jiang
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 986-999 (2023) - [j21]Weidi Sun, Xiaoyong Xue, Yuteng Lu, Jia Zhao, Meng Sun:
HashC: Making deep learning coverage testing finer and faster. J. Syst. Archit. 144: 102999 (2023) - [j20]Chenyang Zhao
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 364-377 (2023) - [j19]Deyang Chen, Zhiwang Guo
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 276-280 (2023) - [j18]Xunming Zhang
Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2226-2230 (2023) - [j17]Zhiwang Guo
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2645-2649 (2023) - [c37]Xiaoyong Xue, Xiyue Zhang, Meng Sun:
kProp: Multi-neuron Relaxation Method for Neural Network Robustness Verification. FSEN 2023: 142-156 - [c36]Xiaoyong Xue, Meng Sun:
Branch and Bound for Sigmoid-Like Neural Network Verification. ICFEM 2023: 137-155 - [c35]Ziyang Shen, Fengshi Tian
NBSSN: A Neuromorphic Binary Single-Spike Neural Network for Efficient Edge Intelligence. ISCAS 2023: 1-5 - [c34]Jianguo Yang, Qing Luo, Xiaoyong Xue, Haijun Jiang, Qiqiao Wu, Zhongze Han, Yue Cao, Yongkang Han, Chunmeng Dou, Hangbing Lv, Qi Liu, Ming Liu:
A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. ISSCC 2023: 498-499 - [c33]Xiangyu Li, Yihao Zhang, Xiaokun Luan, Xiaoyong Xue, Meng Sun:
MedTiny: Enhanced Mediator Modeling Language for Scalable Parallel Algorithms. QRS Companion 2023: 451-460 - 2022
- [j16]Keji Zhou
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 846-857 (2022) - [j15]Keji Zhou
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. Microelectron. J. 125: 105478 (2022) - [j14]Jianguo Yang, Ruijun Lin, Keji Zhou, Yuejun Zhang, Xiaoyong Xue, Hangbing Lv:
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. Microelectron. J. 128: 105550 (2022) - [c32]Fengshi Tian
NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition. ISCAS 2022: 2695-2699 - [c31]Weidi Sun, Xiaoyong Xue, Yuteng Lu, Meng Sun:
HashC: Making DNNs' Coverage Testing Finer and Faster. SETTA 2022: 3-21 - 2021
- [j13]Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng:
Orthogonal obfuscation based key management for multiple IP protection. Integr. 77: 139-150 (2021) - [j12]Keji Zhou
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. IEEE J. Solid State Circuits 56(3): 988-1000 (2021) - [j11]Keji Zhou
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2932-2936 (2021) - [c30]Zhiwang Guo, Deyang Chen, Xiaoyong Xue:
Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS. ASICON 2021: 1-4 - [c29]Yongkang Han, Yulin Zhao, Qiao Hu, Xuanzhi Liu, Bo Peng, Haijun Jiang, Jianguo Yang, Xiaoyong Xue:
Novel 15T SRAM Cell for Low Voltage High Reliability Application. ASICON 2021: 1-4 - [c28]Yujie Huang, Yixuan Liu, Ming-e Jing, Mingyu Wang, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan:
Arbitrary Style Transfer via Learning to Paint in the Feature Domain. ASICON 2021: 1-4 - [c27]Lixing Li
Combining Max Pooling and ReLU Activation Function in Stochastic Computing. ASICON 2021: 1-4 - [c26]Chenyang Zhao
Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. ASICON 2021: 1-4 - [c25]Yujie Huang, Yi Ling, Ming-e Jing, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan:
Fast Style Transfer with High Shape Retention. ISCAS 2021: 1-5 - [c24]Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu, Danian Dong, Feng Zhang, Hangbing Lv, Ming Liu:
24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference. ISSCC 2021: 336-338 - 2020
- [j10]Chao Liu, Jianguo Yang
A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2469-2473 (2020) - [c23]Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng:
Directly Obtaining Matching Points without Keypoints for Image Stitching. ISCAS 2020: 1-5 - [c22]Jinxi Peng, Yuanqi Su, Xiaorong Xue, Yi Li, Bin Liu, Xiaoyong Xue, Aihua Wu:
A Parallel Change Detection Method for Spatiotemporally Multi-Temporal SAR Image Based On Enhance Learning and Wavelet. ISCID 2020: 38-43 - [c21]Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu:
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j9]Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu, Xiaoxin Xu, Qing Luo, Tiancheng Gong, Lu Tai, Peng Yuan, Xiaoyong Xue, Ming Liu, Hangbing Lv:
A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. IEICE Electron. Express 16(12): 20190201 (2019) - [c20]Jiawei Wang, Yuejun Zhang, Pengjun Wang, Zhicun Luan, Xiaoyong Xue, Xiaoyang Zeng, Qiaoyan Yu:
An Orthogonal Algorithm for Key Management in Hardware Obfuscation. AsianHOST 2019: 1-4 - [c19]Yujie Cai, Keji Zhou
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. ASICON 2019: 1-4 - [c18]Jianguo Yang, Xiaowen Li, Qingting Ding, Xiaoyong Xue, Xiaoxin Xu, Qing Luo, Hangbing Lv, Ming Liu:
A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications. ASICON 2019: 1-4 - [c17]Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu:
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. A-SSCC 2019: 29-32 - 2018
- [c16]Keji Zhou
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. A-SSCC 2018: 135-138 - [c15]Jianguo Yang, Xing Li, Tao Wang, Xiaoyong Xue, Zhiliang Hong, Yuanyuan Wang, David Wei Zhang, Hongliang Lu:
A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM. ESSDERC 2018: 54-57 - [c14]Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu:
An Automatic Task Partition Method for Multi-core System. ISCAS 2018: 1-5 - 2017
- [j8]Xiaoyong Xue
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 186-190 (2017) - [c13]Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin:
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. ASICON 2017: 16-19 - [c12]Yun Yin, Tong Li, Xiaoyong Xue:
A 1.0-3.0GHz LTE transmitter with CIM enhancement. ASICON 2017: 1113-1116 - [c11]Jianguo Yang, Yinyin Lin, Yarong Fu, Xiaoyong Xue, B. A. Chen:
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. ISCAS 2017: 1-4 - [c10]Kosei Ueta, Yukikazu Nakamoto, Xiaoyong Xue, Sena Murakami:
Distributed graph database as base of smart world things. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017: 1-5 - 2016
- [j7]Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye
A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express 13(7): 20160195 (2016) - [j6]Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu:
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 336-340 (2016) - [j5]Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1174-1178 (2016) - [c9]Yinyin Lin, Xinyi Hu, Jianguo Yang, Xiaoyong Xue:
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. ISCAS 2016: 13-16 - [c8]Yanqing Zhao, Juan Xu, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jaehwang Sim:
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. ISCAS 2016: 2807-2810 - [c7]Kosei Ueta, Xiaoyong Xue, Yukikazu Nakamoto, Sena Murakami:
A Distributed Graph Database for the Data Management of IoT Systems. iThings/GreenCom/CPSCom/SmartData 2016: 299-304 - 2015
- [c6]Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin:
A low cost and high reliability true random number generator based on resistive random access memory. ASICON 2015: 1-4 - [c5]Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae:
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ASICON 2015: 1-4 - [c4]Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen:
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. ISCAS 2015: 377-380 - 2013
- [j4]Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. IEEE J. Solid State Circuits 48(5): 1315-1322 (2013) - [c3]Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin:
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. ASICON 2013: 1-4 - 2012
- [j3]Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin:
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express 9(12): 1051-1056 (2012) - [c2]Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu:
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. VLSIC 2012: 42-43 - 2011
- [j2]Xiaoyong Xue, Yufeng Xie, Yinyin Lin:
Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express 8(7): 454-459 (2011) - [c1]Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON 2011: 291-294 - 2010
- [j1]Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin:
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. 93-C(12): 1692-1699 (2010)
Coauthor Index
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