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27th DSD 2024: Paris, France
- 27th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, August 28-30, 2024. IEEE 2024, ISBN 979-8-3503-8038-5
- Shima Hosseinzadeh, Suzanne Lancaster, Amirhossein Parvaresh, Cláudia Silva, Dietmar Fey:
Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory. 1-10 - Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das:
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. 11-18 - Maryam Hemmati, Earlene Starling Babette, Julia Shan, Morteza Biglari-Abhari, Smaïl Niar:
Hardware Acceleration of Capsule Networks for Real-Time Applications. 19-25 - Ondrej Stanícek, Filip Kodýtek, Róbert Lórencz:
Counter Power Leakage for Frequency Extraction of Ring Oscillators in ROPUF. 26-32 - Tolga Arul, Nico Mexis, Aleena Elsa George, Florian Frank, Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser:
Investigation of Commercial Off-The-Shelf ReRAM Modules for Use as Runtime-Accessible TRNG. 33-42 - Kévin Quénéhervé, William Pensec, Philippe Tanguy, Rachid Dafali, Vianney Lapôtre:
Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow. 43-50 - Matús Oleksák, Vojtech Miskovský:
Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash Algorithm. 51-56 - Luca Müller, Rolf Drechsler:
SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth. 57-64 - Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt:
Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. 65-72 - Ján Mach, Lukás Kohútka, Pavel Cicák:
Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches. 73-80 - Arvin Delavari, Faraz Ghoreishy, Hadi Shahriar Shahhoseini, Sattar Mirzakuchaki:
A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications. 81-89 - Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Cristian Rossi, Francesco Simula, Piero Vicini:
APEnetX: A Custom NIC for Cluster Interconnects. 90-97 - Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. 98-105 - Jonas Ney, Norbert Wehn:
Achieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA. 106-113 - Carolina Gallardo-Pavesi, Yaime Fernández, Javier E. Soto, Cecilia Hernández, Miguel E. Figueroa:
A Hardware Accelerator for Quantile Estimation of Network Packet Attributes. 114-121 - Bram Van Bolderik, Souradip Sarkar, Vlado Menkovski, Sonia Heemstra, Manil Dev Gomony:
Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers. 122-128 - Lukás Danêk, Martin Novotný:
How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller. 129-136 - Quentin Jayet, Christine Hennebert, Yann Kieffer, Vincent Beroulle:
Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical Threats. 137-144 - Shree Harish S, Debapriya Basu Roy:
Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs. 145-152 - Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, A. J. Acosta:
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. 153-160 - Scott Beamer:
Teaching Agile Hardware Design with Chisel. 161-167 - Martin Schoeberl, Hans Jakob Damsgaard, Luca Pezzarossa, Oliver Keszöcze, Erling Rennemo Jellum:
Hardware Generators with Chisel. 168-175 - Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
DSL-Based SNN Accelerator Design Using Chisel. 176-184 - Franz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf:
ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic. 185-193 - Julio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification. 194-201 - Daniel Suárez
, Víctor Fernández
CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video. 202-209 - Dominika Przewlocka-Rus, Tomasz Kryjak, Marek Gorgon:
PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data. 210-217 - Michael Amar, Lojenaa Navanesan, Asanka P. Sayakkara, Yossi Oren:
Two's Complement: Monitoring Software Control Flow Using Both Power and Electromagnetic Side Channels. 218-226 - Jean-Christophe Le Lann:
An HLS Algorithm for the Direct Synthesis of Complex Control Flow Graphs Into Finite State Machines with Implicit Datapath. 227-233 - Zhifang Sun, Shengjie Jin, Jinxue Duan, Junqiang Jiang, Zebo Peng:
Integrated Mapping and Scheduling Optimization with Genetic Algorithms Based on a Novel Encoding Scheme. 234-241 - Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy:
SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs. 242-249 - Olivier Weppe, Jérôme Chossat, Thibaut Marty, Jean-Christophe Prévotet, Maxime Pelcat:
Streamlined Models of CMOS Image Sensors Carbon Impacts. 250-257 - Saketh Gajawada, Dantu Nandini Devi, Madhav Rao:
HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework. 258-265 - Saba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis, Ahmed Hemani:
Exploration of Custom Floating-Point Formats: A Systematic Approach. 266-273 - Cornelia Wulf, Sergio A. Pertuz, Diana Göhringer:
Hardware-level Access Control and Scheduling of Shared Hardware Accelerators. 274-281 - Alejandro Serrano-Cases, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+. 282-290 - Zhuoer Li, Sébastien Bilavarn:
Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18. 291-297 - Felipe Lisboa Malaquias
Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study. 298-305 - Luca Zulberti, Andrea Monorchio, Matteo Monopoli, Gabriela Mystkowska, Pietro Nannipieri, Luca Fanucci:
SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems. 306-313 - Gabriela Mystkowska, Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci:
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine. 314-318 - Ryudai Iwakami, Bo Peng, Hiroyuki Hanyu, Tasuku Ishigooka, Takuya Azumi:
AUTOSAR AP and ROS 2 Collaboration Framework. 319-326 - Bernando Cabral, Ricardo Venâncio, Pedro Costa, Tiago Fonseca, Luis Lino Ferreira, Ricardo Severino, António Barros:
Multiprotocol Middleware Translator for IoT. 327-334 - Philipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. 335-342 - Noïc Crouzet, Thomas Carle, Christine Rochange:
Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs. 343-350 - Peter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore:
A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. 351-360 - Can Aknesil, Elena Dubrova:
Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure. 361-368 - William Pensec, Vianney Lapôtre, Guy Gogniat:
Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment. 369-376 - Georgios Anagnostopoulos
Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations. 377-384 - João Carlos Resende, Aleksandar Ilic, Ricardo Chaves:
External Memory Protection on FPGA-Based Embedded Systems. 385-393 - Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J. Cazorla:
Event Monitor Validation in High-Integrity Systems. 394-402 - Matthias Stammler, Florian Schade, Jürgen Becker:
Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs. 403-409 - Ensieh Aliagha, Najdet Charaf, Nitin Krishna Venkatesan, Diana Göhringer:
DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge. 410-417 - Federico Nicolás Peccia, Svetlana Pavlitska, Tobias Fleck, Oliver Bringmann:
Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator. 418-426 - Sima Sinaei, Mohammadreza Mohammadi, Rakesh Shrestha, Mina Alibeigi, David Eklund:
PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection. 427-434 - Marko S. Andjelkovic, Nebojsa Maletic, Nicola Miglioranza, Milos Krstic, Enrico Koeck, Jan Buchholz, Maike Taddiken, Markus Fehrenz, Shaden Baradie, Dirk Wübben, Markus Breitbach:
6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications. 435-442 - Himar Fabelo, Raquel León, Emanuele Torti, Santiago Marco, Max Verbers, Yann Falevoz, Yolanda Ramallo-Fariña, Christian Weis, Ana M. Wägner, Eduardo Juárez Martínez, Claudio Rial, Alfonso Lagares, Gustav Burström, Francesco Leporati, Elisa Marenzi, Teresa Cervero, Miquel Moretó, Giovanni Danese, Sveta Zinger, Francesca Manni, Maria Luisa Alvarez-Male, Jesús Morera, Bernardino Clavo, Gustavo M. Callicó, Stratum Consortium:
3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project. 443-450 - Andreas Brokalakis, Iakovos Mavroidis, Konstantinos Georgopoulos, Pavlos Malakonakis, Konstantinos Harteros, Dimitris Andronikou, Yannis Galanomatis, Charalampos Savvakos, Grigorios Chrysos, Sotiris Ioannidis, Ioannis Papaefstathiou:
REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AI. 451-456 - Antonio J. Pérez-Ávila, Miguel A. Mesa-Simón, Antonio Martínez-Olmos, Alberto J. Palma, Nuria López-Ruiz:
Assessment of the Performance of a Commercial Spectral Sensor for Portable and Cost-Effective Multispectral Applications. 457-463 - Laura Quintana, Carlos Vega, Raquel León, Guillermo V. Socorro-Marrero, Samuel Ortega, Gustavo M. Callicó:
Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems. 464-471 - Nerea Marquez-Suarez, Carlos Vega, Raquel León, Gustavo M. Callicó:
Inter-Band Movement Compensation Method for Hyperspectral Images Based on Spectral Scanning Technology. 472-479 - Marco Gazzoni, Emanuele Torti, Elisa Marenzi, Giovanni Danese, Francesco Leporati:
HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images. 480-486 - Mounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker:
Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models. 487-494 - Siddharth Gupta, Salim Ullah, Akash Kumar:
LeQC-At: Learning Quantization Configurations During Adversarial Training for Robust Deep Neural Networks. 495-502 - Yan Chen, Kiyofumi Tanaka:
High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs. 503-511 - Bailian Sun, Mohamed Hassan:
HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost. 512-520 - Matias Vierimaa
Digital Twins Benefits and Challenges from Intelligent Motion Control Point of View. 521-525 - Antonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo:
The TEXTAROSSA Project: Cool all the Way Down to the Hardware. 526-533 - Aimilia Bantouna, Kostas Lampropoulos, Omar Qaise, Andreas Stamoulis, Paris Kitsos, Kostas Poulios, Lampros Raptis, Christos Tranoris:
SAND5G - Security Assessments for Networks and Services in 5G Networks. 534-540 - Tomasz Kryjak:
Event-Based Vision on FPGAs - a Survey. 541-550 - Cornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju:
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery. 551-558 - Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla:
TAP: Task-Aware Profiling on Integrated Systems. 559-567 - Kanish R, Omkar G. Ratnaparkhi, Madhav Rao:
Precision and Power Efficient Piece-Wise-Linear Implementation of Transcendental Functions. 568-575 - Rens Baeyens, Max Cornilly, Dennis Laurijssen, Ron Clijsen, Jean-Pierre Baeyens, Jan Steckel, Walter Daems:
Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists. 576-581 - Paola Vitolo, Gian Domenico Licciardo, Danilo Pau, Rosalba Liguori, Luigi Di Benedetto, Alfredo Rubino:
In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization. 582-587 - Domenico Ragusa, Antonio J. Rodríguez-Almeida, Marco Gazzoni, Emanuele Torti, Elisa Marenzi, Himar Fabelo, Gustavo M. Callicó, Francesco Leporati:
FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing. 588-595 - Daniel Enériz, Antonio J. Rodríguez-Almeida, Himar Fabelo, Gustavo M. Callicó, Nicolás Medrano, Belén Calvo:
Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA. 596-603 - Jakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp:
The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. 604-611 - Alejandro J. Calderón, Aitor Amonarriz, Mar Hernández, Leonidas Kosmidis, Jannis Wolf, Marc Solé Bonet, Matina Maria Trompouki, Mikel Segura, Peio Onaindia:
The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators. 612-619 - Hassan Aboushady, Noemie Beringuier-Boher, Kelly Burke, Philippe Dallemagne, Mario De Biase, Manuel Di Frangia, Virginie Deniau, Enrico Ferrari, Christophe Gaquière, Dominique Morche, Fabio Patrone, Stefano Pesci, Luigi Pomante, Andries Stam, Vincenzo Stornelli, Haralampos-G. Stratigopoulos, Mottaqiallah Taouil, Emmanuel Vaumorin, Jonathan Villain, Sander Steeghs:
Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project. 620-627
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last updated on 2024-12-26 01:00 CET by the dblp team
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