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Wolfgang Ecker
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- affiliation: Infineon Technologies AG, Munich, Germany
- affiliation: Technical University of Munich, Germany
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2020 – today
- 2024
- [c130]Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker:
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE 2024: 1-5 - [c129]Mounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker:
PaGoRi:A Scalable Parallel Golomb-Rice Decoder. DDECS 2024: 67-72 - [c128]Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs. DFT 2024: 1-4 - [c127]Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V. DFT 2024: 1-6 - [c126]Mounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker:
Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models. DSD 2024: 487-494 - [c125]Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. ISQED 2024: 1-8 - [c124]Daniela Sanchez Lopera, Robert Kunzelmann
, Endri Kaja, Wolfgang Ecker:
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. ISQED 2024: 1-8 - [c123]Saruni Fernando, Robert Kunzelmann
Leveraging Large Language Models for the Automated Documentation of Hardware Designs. MECO 2024: 1-6 - [c122]Mayuri Bhadra, Stephanie Ecker, Daniel Albert, Ravindra Ramaiah, Sebastian Prebeck, Wolfgang Ecker:
Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond. NorCAS 2024: 1-7 - [i3]Johannes Schreiner, Daniel Gerl, Robert Kunzelmann, Paritosh Kumar Sinha, Wolfgang Ecker:
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. CoRR abs/2404.05599 (2024) - 2023
- [j13]Lorenzo Servadei
Deep Reinforcement Learning for Optimization at Early Design Stages. IEEE Des. Test 40(1): 43-51 (2023) - [j12]Daniela Sánchez
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. ACM Trans. Design Autom. Electr. Syst. 28(2): 15:1-15:27 (2023) - [c121]Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu:
Special Session: Machine Learning for Embedded System Design. CODES+ISSS 2023: 28-37 - [c120]Saranyu Chattopadhyay
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. DAC 2023: 1-6 - [c119]Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter
Bits, Flips and RISCs. DDECS 2023: 140-149 - [c118]Mounika Vaddeboina, Endri Kaja, Alper Yilmayer, Sebastian Prebeck, Wolfgang Ecker:
Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications. DSD 2023: 227-234 - [c117]Johannes Schreiner, Vasundhara Raje Gontia, Sebastian Prebeck, Wolfgang Ecker:
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. MBMV 2023: 1-12 - [c116]Endri Kaja, Nicolas Gerlin, Robert Kunzelmann
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC 2023: 508-515 - [c115]Daniela Sanchez Lopera
Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations. MLCAD 2023: 1-6 - [c114]Johannes Kappes, Robert Kunzelmann
Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. NorCAS 2023: 1-7 - [c113]Gabriel Rutsch, Konrad Maier, Wolfgang Ecker:
FPGA-implementation techniques to efficiently test application readiness of mixed-signal products. VLSI-SoC 2023: 1-6 - 2022
- [j11]Daniela Sanchez Lopera
Early RTL delay prediction using neural networks. Microprocess. Microsystems 94: 104671 (2022) - [j10]Rana Elnaggar
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2066-2079 (2022) - [j9]Steven Herbst
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2223-2236 (2022) - [c112]Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic
The Scale4Edge RISC-V Ecosystem. DATE 2022: 808-813 - [c111]Endri Kaja, Nicolas Gerlin, Monideep Bora
MetaFS: Model-driven Fault Simulation Framework. DFT 2022: 1-4 - [c110]Daniela Sanchez Lopera
Applying GNNs to Timing Estimation at RTL. ICCAD 2022: 3:1-3:8 - [c109]Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker:
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. MBMV 2022: 1-9 - [c108]Christian Lück, Daniela Sanchez Lopera, Sven Wenzek, Wolfgang Ecker:
Industrial Experience with Open-Source EDA Tools. MLCAD 2022: 143 - [c107]Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker:
A framework that enables systematic analysis of mixed-signal applications on FPGA. RSP 2022: 50-56 - [c106]Sebastian Siegfried Prebeck, Wafic Lawand
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions. SAMOS 2022: 267-282 - [c105]Nicolas Gerlin, Endri Kaja, Monideep Bora
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC 2022: 1-6 - [c104]Endri Kaja, Nicolas Gerlin, Monideep Bora
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC 2022: 1-6 - [i2]Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora
MetFI: Model-driven Fault Simulation Framework. CoRR abs/2204.13183 (2022) - 2021
- [c103]Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder
Automated HW/SW co-design for edge AI: state, challenges and steps ahead. CODES+ISSS 2021: 11-20 - [c102]Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker:
ISA Modeling with Trace Notation for Context Free Property Generation. DAC 2021: 619-624 - [c101]Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker:
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT 2021: 1-6 - [c100]Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker:
On Self-Verifying DSL Generation for Embedded Systems Automation. MBMV 2021: 1-7 - [c99]Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker:
Extending Verilator to Enable Fault Simulation. MBMV 2021: 1-6 - [c98]Daniela Sanchez Lopera
A Survey of Graph Neural Networks for Electronic Design Automation. MLCAD 2021: 1-6 - [c97]Daniela Sanchez Lopera
RTL Delay Prediction Using Neural Networks. NorCAS 2021: 1-7 - [c96]Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera
Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC 2021: 1-6 - [c95]Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera
Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) 2021: 49-70 - 2020
- [j8]Lorenzo Servadei
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. IEEE Trans. Computers 69(6): 856-867 (2020) - [c94]Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
Gap-free Processor Verification by S2QED and Property Generation. DATE 2020: 526-531 - [c93]Michael Werner, Igli Zeraliu, Zhao Han, Sebastian Siegfried Prebeck, Lorenzo Servadei, Wolfgang Ecker:
Optimized HW/FW Generation from an Abstract Register Interface Model. DSD 2020: 35-39 - [c92]Antti Rautakoura
Kamel: IP-XACT compatible intermediate meta-model for IP generation. DSD 2020: 325-331 - [c91]Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille:
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. ACM Great Lakes Symposium on VLSI 2020: 405-410 - [c90]Vijay Deep Bhatt, Wolfgang Ecker, Volkan Esen, Zhao Han, Daniela Sanchez Lopera
SoC Design Automation with ML - It's Time for Research. MLCAD 2020: 35-36 - [c89]Lorenzo Servadei, Jiapeng Zheng, Jose A. Arjona-Medina, Michael Werner, Volkan Esen, Sepp Hochreiter, Wolfgang Ecker, Robert Wille:
Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning. MLCAD 2020: 37-42 - [c88]Michael Werner, Lorenzo Servadei, Robert Wille, Wolfgang Ecker:
Automatic compiler optimization on embedded software through k-means clustering. MLCAD 2020: 157-162
2010 – 2019
- 2019
- [j7]Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille:
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. Microprocess. Microsystems 71 (2019) - [c87]Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker:
Increasing Soft Error Resilience by Software Transformation. DAC 2019: 199 - [c86]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE 2019: 1000-1005 - [c85]Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille:
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. DATE 2019: 1277-1280 - [c84]Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei:
Embedded Systems' Automation following OMG's Model Driven Architecture Vision. DATE 2019: 1301-1306 - [c83]Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda:
Formal Verification Methodology in an Industrial Setup. DSD 2019: 610-614 - [c82]Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz:
How to Keep 4-Eyes Principle in a Design and Property Generation Flow. MBMV 2019: 1-6 - [c81]Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker:
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. NORCAS 2019: 1-7 - [i1]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR abs/1902.01494 (2019) - 2018
- [c80]Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker:
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. DSD 2018: 413-420 - [c79]Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt
Analog fault simulation automation at schematic level with random sampling techniques. DTIS 2018: 1-4 - [c78]Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille:
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. CIMA@ICTAI 2018: 14-27 - [c77]Keerthikumara Devarajegowda, Wolfgang Ecker:
Meta-model Based Automation of Properties for Pre-Silicon Verification. VLSI-SoC 2018: 231-236 - 2017
- [c76]Keerthikumara Devarajegowda, Wolfgang Ecker:
On generation of properties from specification. HLDVT 2017: 95-98 - [c75]Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD 2017: 1019-1025 - [c74]Daniel Mueller-Gritschneder
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP 2017: 79-84 - [p1]Wolfgang Ecker, Johannes Schreiner:
Metamodeling and Code Generation in the Hardware/Software Interface Domain. Handbook of Hardware/Software Codesign 2017: 1051-1091 - 2016
- [c73]Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello:
Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation. DSD 2016: 364-371 - [c72]Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Bogdan-Andrei Tabacaru:
Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes. DSN Workshops 2016: 226-229 - [c71]Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello:
Fault-effect analysis on system-level hardware modeling using virtual prototypes. FDL 2016: 1-7 - [c70]Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Design centric modeling of digital hardware. HLDVT 2016: 46-52 - [c69]Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Where formal verification can help in functional safety analysis. ICCAD 2016: 85 - [c68]Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello:
Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. SAFECOMP Workshops 2016: 144-156 - [c67]Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Efficient handling of the fault space in functional safety analysis utilizing formal methods. VLSI-SoC 2016: 1-7 - [c66]Wolfgang Ecker, Johannes Schreiner:
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. VLSI-SoC 2016: 1-6 - [c65]Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker:
Automatically comparing analog behavior using Earth Mover's Distance. VLSI-SoC 2016: 1-8 - [c64]Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello:
Speeding up safety verification by fault abstraction and simulation to transaction level. VLSI-SoC 2016: 1-6 - [c63]Johannes Schreiner, Wolfgang Ecker:
Digital Hardware Design Based on Metamodels and Model Transformations. VLSI-SoC (Selected Papers) 2016: 83-107 - [c62]Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker:
Earth Mover's Distance as a Comparison Metric for Analog Behavior. VLSI-SoC (Selected Papers) 2016: 173-191 - 2015
- [c61]Moomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse:
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. DAC 2015: 1:1-1:6 - [c60]Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh:
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. DATE 2015: 1698-1707 - 2014
- [c59]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
A transaction-oriented UVM-based library for verification of analog behavior. ASP-DAC 2014: 806-811 - [c58]Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal:
Metasynthesis for Designing Automotive SoCs. DAC 2014: 71:1-71:6 - [c57]Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC 2014: 113:1-113:6 - [c56]Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal:
The metamodeling approach to system level synthesis. DATE 2014: 1-2 - 2013
- [c55]Rainer Findenig, Thomas Leitner, Wolfgang Ecker:
Transaction-Level Modeling and Refinement Using State Charts. EUROCAST (1) 2013: 134-141 - [c54]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Comparison of analog transactions using statistics. ISSoC 2013: 1-6 - [c53]Juergen Karmann, Wolfgang Ecker:
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. PATMOS 2013: 45-50 - 2012
- [c52]Wolfgang Müller, Wolfgang Ecker:
Testbenches for advanced TLM verification. CODES+ISSS 2012: 305-306 - [c51]Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu:
SystemC as completing pillar in industrial OVM based verification environments. CODES+ISSS 2012: 307-312 - [c50]Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große
The system verification methodology for advanced TLM verification. CODES+ISSS 2012: 313-322 - [c49]Rainer Findenig, Thomas Leitner, Wolfgang Ecker:
Single-source hardware modeling of different abstraction levels with State Charts. HLDVT 2012: 41-48 - 2011
- [c48]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Analog transaction level modeling. HLDVT 2011: 82 - 2010
- [c47]Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten:
TLM+ modeling of embedded HW/SW systems. DATE 2010: 75-80 - [c46]Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jürgen Mössinger, Andreas von Schwerin:
Panel Session - Who Is Closing the embedded software design gap? DATE 2010: 932 - [c45]Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker:
Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. HLDVT 2010: 97-102 - [c44]Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten:
Model reduction techniques for the formal verification of hardware dependent software. HLDVT 2010: 148-153 - [c43]Rainer Findenig, Wolfgang Ecker:
State chart refinement validation from approximately timed to cycle callable models. SoC 2010: 72-75
2000 – 2009
- 2009
- [c42]Wolfgang Ecker, Stefan Heinen, Michael Velten:
Using a dataflow abstracted virtual prototype for HdS-design. ASP-DAC 2009: 293-300 - 2008
- [c41]Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin:
Industrial IP Integration Flows based on IP-XACT Standards. DATE 2008: 32-37 - 2007
- [c40]Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE 2007: 767-772 - [c39]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE 2007: 894-899 - [c38]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertion Refinement. IESS 2007: 1-14 - 2006
- [c37]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Case Study on Transaction Level Modeling. FDL 2006: 209-215 - [c36]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit:
IP Library For Temporal SystemC Assertions. FDL 2006: 301-309 - [c35]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Specification Language for Transaction Level Assertions. HLDVT 2006: 77-84 - [c34]Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertions. ICCD 2006: 286-293 - [c33]Wolfgang Ecker, Volkan Esen, Michael Hull:
Execution semantics and formalisms for multi-abstraction TLM assertions. MEMOCODE 2006: 93-102 - 2005
- [c32]Wolfgang Ecker, Lothar Schrader:
Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. GI Jahrestagung (1) 2005: 313 - 2004
- [j6]Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer:
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. IEEE Des. Test Comput. 21(6): 464-471 (2004) - [c31]Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi:
SystemVerilog: Interface Based Design. FDL 2004: 505-518 - [c30]Martin Zambaldi, Wolfgang Ecker:
Extending the RASSP model for Verification. FDL 2004: 536-544 - [c29]Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Müller:
The Formal Simulation Semantics of SystemVerilog. FDL 2004: 568-578 - [c28]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi:
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC 2004: 129-135 - [c27]Martin Zambaldi, Wolfgang Ecker:
How to Bridge the Gap Between Simulationand Test. ITC 2004: 1091-1099 - [c26]Martin Zambaldi, Wolfgang Ecker:
Ein orthogonales Schema für die Klassifikation der Modellierungsabstraktion von digitalen Systemen. MBMV 2004: 96-105 - 2003
- [c25]Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker:
Re-use-centric architecture for a fully accelerated testbench environment. DAC 2003: 372-375 - [c24]Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi:
Platform-Based Testbench Generation. DATE 2003: 11038-11045 - [c23]Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer:
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. IPDPS 2003: 187 - [c22]Fanny Garnier, Wolfgang Ecker:
Incremental Design: A VHDL based Case Study. MBMV 2003: 81-92 - [c21]Martin Zambaldi, Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn:
An Enhanced Environment for Multi-Level Simulation. MBMV 2003: 174-183 - 2002
- [j5]Matthias Bauer, Wolfgang Ecker, Renate Henftling, Martin Zambaldi, Andreas Zinn:
Verifikation und Wiederverwendung (Verification and Re-Use). Informationstechnik Tech. Inform. 44(2): 108-114 (2002) - 2001
- [c20]Wolfgang Ecker:
Hardware-basierter Hardware-Entwurf. MBMV (1) 2001: 59-61 - 2000
- [j4]André Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker:
Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). Informationstechnik Tech. Inform. 42(5): 43- (2000) - [c19]Thomas Schneider, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker:
An Open VHDL-AMS Simulation Framework. BMAS 2000: 89-94 - [c18]Matthias Bauer, Wolfgang Ecker, Andreas Zinn:
Graphische Spezifikation und Analyse funktionaler Testabläufe mit MSCs der UML. MBMV 2000: 113-120 - [c17]Wolfgang Ecker, Mike Heuchling, Jochen Mades, Thomas Schneider, André Windisch, Ke Yang:
VXML: VHDL Hardware Design Representation in XML. MBMV 2000: 129-140 - [c16]Jochen Mades, Thomas Schneider, Manfred Glesner, André Windisch, Wolfgang Ecker:
A JAVA-Based Mixed-Signal Design Environment. SBCCI 2000: 301-306
1990 – 1999
- 1999
- [c15]Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn:
A Method for Accelerating Test Environments. EUROMICRO 1999: 1477-1480 - [c14]André Windisch, Thomas Schneider, Ke Yang, Jochen Mades, Wolfgang Ecker:
A scalable multithreaded compiler front-end. PARCO 1999: 722-729 - 1998
- [j3]Wolfgang Ecker, Yvonne Fritzsch, Viktor Preis:
Reuse-Potentiale im Hardware-Entwurf. Informationstechnik Tech. Inform. 40(3): 37-41 (1998) - 1997
- [c13]Matthias Bauer, Wolfgang Ecker:
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. DAC 1997: 774-779 - [c12]Michael Mrva, Mike Heuchling, Wolfgang Ecker:
The Shall-Prototype-Test Development model. ECBS 1997: 385-391 - 1996
- [j2]Manfred Selz, Wolfgang Ecker, Eugenio Villar
VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. 42(2): 105-116 (1996) - [j1]Wolfgang Ecker:
Verification methods for VHDL RTL-subroutines. J. Syst. Archit. 42(2): 117-128 (1996) - [c11]Claus Schneider, Wolfgang Ecker:
Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. EURO-DAC 1996: 509-514 - 1995
- [c10]Wolfgang Ecker:
Semi-dynamic scheduling of synchronization-mechanisms. EURO-DAC 1995: 374-379 - [c9]Wolfgang Ecker, Manfred Huber:
VHDL-based communication and synchronization synthesis. EURO-DAC 1995: 458-462 - [c8]Wolfgang Ecker:
A classification of design steps and their verification. EURO-DAC 1995: 536-541 - 1994
- [c7]Wolfgang Ecker, Manfred Glesner, Andreas Vombach:
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC 1994: 624-629 - 1993
- [c6]Wolfgang Ecker, Sabine März:
System-Level Specification and Design Using VHDL: A Case Study. CHDL 1993: 505-522 - [c5]Wolfgang Ecker:
Using VHDL for HW/SW co-specification. EURO-DAC 1993: 500-505 - [c4]Wolfgang Ecker, Michael Hofmeister:
State look ahead technique for cycle optimization of interacting finite state Moore machines. ICCAD 1993: 392-397 - 1992
- [c3]Wolfgang Ecker:
Towards a common RT-level subset of VHDL. EURO-DAC 1992: 682 - [c2]Wolfgang Ecker, Sabine März:
Subtype concept of VHDL for synthesis constraints. EURO-DAC 1992: 720-725 - [c1]Wolfgang Ecker, Michael Hofmeister:
The design cube: a new model for VHDL designflow representation. EURO-DAC 1992: 752-757
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