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23rd ETS 2018: Bremen, Germany
- 23rd IEEE European Test Symposium, ETS 2018, Bremen, Germany, May 28 - June 1, 2018. IEEE 2018, ISBN 978-1-5386-3728-9
- Xuanle Ren, R. D. (Shawn) Blanton, Vítor Grade Tavares
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Detection of IJTAG attacks using LDPC-based feature reduction and machine learning. 1-6 - Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker
Online prevention of security violations in reconfigurable scan networks. 1-6 - Sukanta Bhattacharjee, Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty
Locking of biochemical assays for digital microfluidic biochips. 1-6 - Jan Schat:
ADC test methods using an impure stimulus: A survey. 1-5 - Krzysztof Jurga, Stephen Sunter:
Measuring mixed-signal test stimulus quality. 1-6 - Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel:
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. 1-6 - Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. 1-6 - Yumin Zhou, Sebastian Burg, Oliver Bringmann, Wolfgang Rosenstiel:
A software reconfigurable assertion checking unit for run-time error detection. 1-6 - Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker
Towards the formal verification of security properties of a Network-on-Chip router. 1-6 - Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty
Design of fault-tolerant neuromorphic computing systems. 1-9 - Stefan Holst, Ruijun Ma
The impact of production defects on the soft-error tolerance of hardened latches. 1-6 - Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen:
Modeling and testing comparison faults of memristive ternary content addressable memories. 1-6 - Dhruv Patel
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. 1-6 - Josep Balasch, Florent Bernard, Viktor Fischer, Milos Grujic
Design and testing methodologies for true random number generators towards industry certification. 1-10 - Imed Jani, Didier Lattard, Pascal Vivet
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. 1-6 - Irith Pomeranz, Srikanth Venkataraman:
Interconnect-aware tests to complement gate-exhaustive tests. 1-6 - Shreyas Pramod Dixit, Divyeshkumar Dhanjibhai Vora, Ke Peng:
Challenges in Cell-Aware Test. 1-6 - Haralampos-G. D. Stratigopoulos:
Machine learning applications in IC testing. 1-10 - Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi:
Device aging: A reliability and security concern. 1-10 - Jan Peleska:
Model-based avionic systems testing for the airbus family. 1-10 - Irith Pomeranz:
Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests. 1-2 - Po-Yao Chuang
Covering hard-to-detect defects by thermal quorum sensing. 1-2 - Sujay Pandey, Suvadeep Banerjee
ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks. 1-2 - Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. 1-2 - Xiaotong Cui
Hardware Trojan detection using path delay order encoding with process variation tolerance. 1-2 - Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. 1-2 - Ciprian V. Pop, Andi Buzo
Methodology for determining the influencing factors of lifetime variation for power devices. 1-2 - Tong-Yu Hsieh, Shang-En Chan, Chi-Hsuan Ho:
On no-reference on-line error-tolerability testing for videos. 1-2 - Yasamin Moradi, Krishnendu Chakrabarty
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis. 1-2 - Daniele Rossi
Recycled IC detection through aging sensor. 1-2 - Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen
Automatic generation of in-circuit tests for board assembly defects. 1-2 - Sarah Azimi
On the mitigation of single event transients on flash-based FPGAs. 1-2
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