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Cheng-Wen Wu
Person information
- affiliation: Southern Taiwan University of Science and Technology, Tainan, Taiwan
- affiliation (1988 - 2023): National Tsing Hua University, Hsinchu, Taiwan
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2020 – today
- 2024
- [c164]Cheng-Wen Wu, Shi-Yu Huang:
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. ETS 2024: 1-2 - 2023
- [j88]Pai-Yu Tan
, Cheng-Wen Wu
A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1994-2007 (2023) - [c163]Po-Yao Chuang
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c162]Pai-Yu Tan
A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. ASP-DAC 2023: 651-656 - [c161]Po-Yao Chuang
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - 2022
- [j87]Wei-Han Chen
Impact Position Estimation for Baseball Batting with a Force-Irrelevant Vibration Feature. Sensors 22(4): 1553 (2022) - [j86]Cheng-Wen Wu
Enhancing Fan Engagement in a 5G Stadium With AI-Based Technologies and Live Streaming. IEEE Syst. J. 16(4): 6590-6601 (2022) - [c160]Kuan-Hsun Duh, Cheng-Wen Wu
Aging Impact of Power MOSFETs in Charger with Different Operation Frequency. ATS 2022: 54-59 - [c159]Yu-You Chou, Cheng-Wen Wu
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration. ATS 2022: 66-71 - [c158]Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. ITC 2022: 92-99 - [c157]Ya-Chi Cheng, Pai-Yu Tan
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. ITC 2022: 601-608 - [c156]Ya-Chi Cheng, Pai-Yu Tan
A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. ITC-Asia 2022: 19-24 - [c155]Shian-Yu Lin, Pai-Yu Tan
Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. ITC-Asia 2022: 25-30 - [c154]Pai-Yu Tan
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT 2022: 1-4 - [c153]Hong-Hao Wang, Po-Yao Chuang
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. VLSI-DAT 2022: 1-4 - 2021
- [j85]Yu-Rong Jian
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test 38(5): 82-89 (2021) - [c152]Pai-Yu Tan
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. DATE 2021: 575-580 - 2020
- [c151]Po-Yao Chuang
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC 2020: 1-6 - [c150]Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS 2020: 1-6 - [c149]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC 2020: 1-9 - [c148]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia 2020: 13-18 - [i2]Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu:
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR abs/2003.06310 (2020)
2010 – 2019
- 2019
- [j84]Cheng-Wen Wu
The Last Byte: Baseball and Testing. IEEE Des. Test 36(6): 88 (2019) - [c147]Michiko Inoue, Xiaowei Li
Asian Test Symposium - Past, Present and Future -. ITC 2019: 1-4 - 2018
- [c146]Ying-Cih Kao, Cheng-Wen Wu
A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning. ACSSC 2018: 2060-2064 - [c145]Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu
A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit. ATS 2018: 19-24 - [c144]Po-Yao Chuang
Covering hard-to-detect defects by thermal quorum sensing. ETS 2018: 1-2 - [c143]Su-Fu Kuo, Cheng-Wen Wu
Symbiotic Controller Design Using a Memory-Based FSM Model. ISIE 2018: 874-879 - [c142]Erik Jan Marinissen
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC 2018: 1-10 - [c141]Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. ITC-Asia 2018: 19-24 - 2017
- [j83]Zhi-Yong Liu
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test 34(2): 69-78 (2017) - [j82]Kai-Li Wang
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34(3): 50-58 (2017) - [j81]Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66(8): 1293-1301 (2017) - [c140]Pok Man Preston Law, Cheng-Wen Wu
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. ATS 2017: 5-10 - [c139]Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu
Highly reliable and low-cost symbiotic IOT devices and systems. ITC 2017: 1-10 - [c138]Po-Yao Chuang
Cell-aware test generation time reduction by using switch-level ATPG. ITC-Asia 2017: 27-32 - [c137]Cheng-Wen Wu
Symbiotic system models for efficient IGT system design and test. ITC-Asia 2017: 71-76 - [c136]Cheng-Wen Wu:
Can IOT make semiconductor great again? VLSI-DAT 2017: 1 - 2016
- [j80]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33(2): 30-39 (2016) - [j79]Bing-Yang Lin, Cheng-Wen Wu
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65(3): 770-780 (2016) - [c135]Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. ATS 2016: 156-160 - [c134]Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. ATS 2016: 197-202 - [c133]Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC 2016: 58:1-58:6 - [c132]Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu
A fast sweep-line-based failure pattern extractor for memory diagnosis. ETS 2016: 1-6 - [c131]Cheng-Wen Wu:
Is IoT coming to the rescue of semiconductor? ETS 2016: 1 - 2015
- [j78]Wei-Chung Cheng
YM500v2: a small RNA sequencing (smRNA-seq) database for human cancer miRNome research. Nucleic Acids Res. 43(Database-Issue): 862-867 (2015) - [c130]Bing-Yang Lin, Cheng-Wen Wu
System-level test coverage prediction by structural stress test data mining. VLSI-DAT 2015: 1-4 - [c129]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2014
- [j77]Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31(4): 16-26 (2014) - [j76]Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1356-1369 (2014) - [j75]Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 207-219 (2014) - [j74]Chun-Chuan Chi, Erik Jan Marinissen
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - [c128]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c127]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC 2014: 1-7 - 2013
- [j73]Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu
Generalization of an Enhanced ECC Methodology for Low Power PSRAM. IEEE Trans. Computers 62(7): 1318-1331 (2013) - [j72]Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2343-2351 (2013) - [j71]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [j70]Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 443-453 (2013) - [j69]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 465-474 (2013) - [j68]Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu
Write Current Self-Configuration Scheme for MRAM Yield Improvement. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1260-1270 (2013) - [c126]Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC 2013: 429-434 - [c125]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium 2013: 1-6 - [c124]Hsiu-Chuan Shih, Cheng-Wen Wu
An enhanced double-TSV scheme for defect tolerance in 3D-IC. DATE 2013: 1486-1489 - [c123]Cheng-Wen Wu:
Holistic approach to low-power system design. ISLPED 2013: 2 - [c122]Yuriy Shiyanovskii, Christos A. Papachristou
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs. ISQED 2013: 24-29 - [c121]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c120]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c119]Chun-Chuan Chi, Cheng-Wen Wu
3D-IC interconnect test, diagnosis, and repair. VTS 2013: 1-6 - [c118]Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. VTS 2013: 1 - [c117]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [c116]Cheng-Wen Wu
On test and repair of 3D random access memory. ASP-DAC 2012: 744-749 - [c115]Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC 2012: 1-9 - [c114]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - [c113]Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4 - [c112]Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu
Cost modeling and analysis for interposer-based three-dimensional IC. VTS 2012: 108-113 - [c111]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS 2012: 234-239 - 2011
- [j67]Mincent Lee, Li-Ming Denq, Cheng-Wen Wu
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 919-929 (2011) - [j66]Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1346-1356 (2011) - [j65]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2184-2194 (2011) - [c110]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c109]Chun-Chuan Chi, Erik Jan Marinissen
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c108]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - [c107]Chun-Chuan Chi, Erik Jan Marinissen
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c106]Chun-Chuan Chi, Erik Jan Marinissen
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - [c105]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - [c104]Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu
Training-based forming process for RRAM yield improvement. VTS 2011: 146-151 - [c103]Cheng-Wen Wu
Special session: Hot topic design and test of 3D and emerging memories. VTS 2011: 328 - 2010
- [j64]Yu-Tsao Hsing
Economic Analysis of the HOY Wireless Test Methodology. IEEE Des. Test Comput. 27(3): 20-30 (2010) - [j63]Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
Built-In Self-Repair Schemes for Flash Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1243-1256 (2010) - [j62]Chih-Yen Lo, Yu-Tsao Hsing
SOC Test Architecture and Method for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1645-1649 (2010) - [j61]Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 184-193 (2010) - [j60]Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu
Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 541-552 (2010) - [j59]Chen-Hsing Wang, Chieh-Lin Chuang, Cheng-Wen Wu
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 553-563 (2010) - [j58]Mao-Yin Wang, Cheng-Wen Wu
A Mesh-Structured Scalable IPsec Processor. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 725-731 (2010) - [j57]Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu
Diagnosis of MRAM Write Disturbance Fault. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1762-1766 (2010) - [c102]Jin-Fu Li, Cheng-Wen Wu
Is 3D integration an opportunity or just a hype? ASP-DAC 2010: 541-543 - [c101]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c100]Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394 - [c99]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng
An error tolerance scheme for 3D CMOS imagers. DAC 2010: 917-922 - [c98]Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu
Fast identification of operating current for toggle MRAM by spiral search. DAC 2010: 923-928 - [c97]Ching-Yi Chen, Cheng-Wen Wu:
An adaptive code rate EDAC scheme for random access memory. DATE 2010: 735-740 - [c96]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348 - [c95]Chun-Chuan Chi, Cheng-Wen Wu
A low-cost and scalable test architecture for multi-core chips. ETS 2010: 30-35 - [c94]Po-Yuan Chen, Cheng-Wen Wu
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. VTS 2010: 263-268
2000 – 2009
- 2009
- [j56]Li-Ming Denq, Yu-Tsao Hsing
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. IEEE Des. Test Comput. 26(2): 64-73 (2009) - [c93]Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium 2009: 287-292 - [c92]Po-Yuan Chen, Cheng-Wen Wu
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. Asian Test Symposium 2009: 450-455 - [c91]Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. VTS 2009: 53-58 - 2008
- [j55]Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu
A Systematic Approach to Memory Test Time Reduction. IEEE Des. Test Comput. 25(6): 560-570 (2008) - [j54]Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu
Write Disturbance Modeling and Testing for MRAM. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 277-288 (2008) - [c90]Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS 2008: 245-250 - [c89]Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu
Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault. ATS 2008: 417-422 - 2007
- [j53]Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu
Economic Aspects of Memory Built-in Self-Repair. IEEE Des. Test Comput. 24(2): 164-172 (2007) - [j52]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. 24(4): 386-396 (2007) - [j51]Yen-Lin Peng, Cheng-Wen Wu
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. 1(6): 716-723 (2007) - [j50]Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1101-1113 (2007) - [j49]Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 541-545 (2007) - [c88]Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu:
Test Education in the Global Economy. ATS 2007: 53 - [c87]Li-Ming Denq, Cheng-Wen Wu:
A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. ATS 2007: 349-354 - [c86]Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu:
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS 2007: 355-360 - [c85]Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu
Diagnosis for MRAM write disturbance fault. ITC 2007: 1-9 - [c84]Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
A prototype of a wireless-based test system. SoCC 2007: 225-228 - [c83]Yu-Tsao Hsing
SDRAM Delay Fault Modeling and Performance Testing. VTS 2007: 53-58 - [i1]Cheng-Wen Wu:
SOC Testing Methodology and Practice. CoRR abs/0710.4669 (2007) - 2006
- [j48]Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 34-42 (2006) - [c82]Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu
An Enhanced SRAM BISR Design with Reduced Timing Penalty. ATS 2006: 25-30 - [c81]Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495 - [c80]Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu
An Enhanced EDAC Methodology for Low Power PSRAM. ITC 2006: 1-10 - [c79]Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu
Testing MRAM for Write Disturbance Fault. ITC 2006: 1-9 - [c78]Mu-Hsien Hsu, Yu-Tsao Hsing
Fault-Pattern Oriented Defect Diagnosis for Flash Memory. MTDT 2006: 3-8 - [c77]Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. VTS 2006: 114-119 - [c76]Cheng-Wen Wu:
Session Abstract. VTS 2006: 128-129 - 2005
- [j47]Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 742-745 (2005) - [c75]Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
A configurable AES processor for enhanced security. ASP-DAC 2005: 361-366 - [c74]Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Design and test of a scalable security processor. ASP-DAC 2005: 372-375 - [c73]Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu
Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium 2005: 182-187 - [c72]Cheng-Wen Wu
SOC Testing Methodology and Practice. DATE 2005: 1120-1121 - [c71]Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu:
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. DFT 2005: 81-92 - [c70]Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu
A systematic approach to reducing semiconductor memory test time in mass production. MTDT 2005: 97-102 - [c69]Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu
Flash Memory Built-In Self-Diagnosis with Test Mode Control. VTS 2005: 15-20 - [c68]Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
A BIST Scheme for FPGA Interconnect Delay Faults. VTS 2005: 201-206 - 2004
- [j46]Bin-Hong Lin, Cheng-Wen Wu
Efficient and Economical Test Equipment Setup Using Procorrelation. IEEE Des. Test Comput. 21(1): 34-43 (2004) - [j45]Chih-Pin Su, Cheng-Wen Wu
A Graph-Based Approach to Power-Constrained SOC Test Scheduling. J. Electron. Test. 20(1): 45-60 (2004) - [c67]Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu:
SRAM delay fault modeling and test algorithm development. ASP-DAC 2004: 104-109 - [c66]Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC 2004: 456-458 - [c65]Hao-Chiao Hong
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. Asian Test Symposium 2004: 62-67 - [c64]Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu:
On Test and Diagnostics of Flash Memories. Asian Test Symposium 2004: 260-265 - [c63]Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang:
Fail Pattern Identification for Memory Built-In Self-Repair. Asian Test Symposium 2004: 366-371 - [c62]Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu:
Failure Factor Based Yield Enhancement for SRAM Designs. DFT 2004: 20-28 - [c61]Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT 2004: 478-486 - [c60]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli. ITC 2004: 124-133 - [c59]Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT 2004: 65-69 - 2003
- [j44]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
A high-throughput low-cost AES processor. IEEE Commun. Mag. 41(12): 86-91 (2003) - [j43]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. J. Electron. Test. 19(2): 207-215 (2003) - [j42]Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu:
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19(4): 571-587 (2003) - [j41]Shao-Hui Shieh, Cheng-Wen Wu:
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. J. Inf. Sci. Eng. 19(6): 1015-1039 (2003) - [j40]Hao-Chiao Hong
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 553-566 (2003) - [j39]Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. 52(4): 386-399 (2003) - [j38]Jin-Hua Hong, Cheng-Wen Wu
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 474-484 (2003) - [c58]Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
Design of a scalable RSA and ECC crypto-processor. ASP-DAC 2003: 495-498 - [c57]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A highly efficient AES cipher chip. ASP-DAC 2003: 561-562 - [c56]Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
Defect Oriented Fault Analysis for SRAM. Asian Test Symposium 2003: 256-261 - [c55]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
A Processor-Based Built-In Self-Repair Design for Embedded Memories. Asian Test Symposium 2003: 366-371 - [c54]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c53]Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang:
Combinational circuit fault diagnosis using logic emulation. ISCAS (5) 2003: 549-552 - [c52]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38 - [c51]Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC 2003: 393-402 - [c50]Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT 2003: 53- - [c49]Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253 - 2002
- [j37]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. J. Electron. Test. 18(4-5): 515-527 (2002) - [j36]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. 18(6): 637-647 (2002) - [j35]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu
A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5): 69-81 (2002) - [j34]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 480-490 (2002) - [j33]Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1328-1336 (2002) - [j32]Jin-Fu Li, Cheng-Wen Wu
Efficient FFT network testing and diagnosis schemes. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 267-278 (2002) - [c48]Hao-Chiao Hong
On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium 2002: 49- - [c47]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c46]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - [c45]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu
A Hierarchical Test Scheme for System-On-Chip Designs. DATE 2002: 486-490 - [c44]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141 - [c43]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu:
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW 2002: 262- - [c42]Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC 2002: 37-46 - [c41]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT 2002: 68- - [c40]Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288 - [c39]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
Testing and Diagnosing Embedded Content Addressable Memories. VTS 2002: 389-394 - 2001
- [j31]Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu:
VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem. J. Inf. Sci. Eng. 17(6): 967-980 (2001) - [j30]Shih-Arn Hwang, Cheng-Wen Wu
Unified VLSI systolic array design for LZ data compression. IEEE Trans. Very Large Scale Integr. Syst. 9(4): 489-499 (2001) - [c38]Ching-Hong Tsai, Cheng-Wen Wu:
Processor-programmable memory BIST for bus-connected embedded memories. ASP-DAC 2001: 325-330 - [c37]Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu:
RSA cryptosystem design based on the Chinese remainder theorem. ASP-DAC 2001: 391-395 - [c36]Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96 - [c35]Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- - [c34]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306 - [c33]Jin-Fu Li, Cheng-Wen Wu
Memory fault diagnosis by syndrome compression. DATE 2001: 97-101 - [c32]Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu:
A Profit Evaluation System (PES) for logic cores at early design stage. ICECS 2001: 1491-1494 - [c31]Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767 - [c30]Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. VTS 2001: 225-230 - 2000
- [j29]Chih-Yuang Su, Cheng-Wen Wu:
A Probabilistic Model for Path Delay Fault Testing. J. Inf. Sci. Eng. 16(5): 783-794 (2000) - [j28]Kun-Jin Lin, Cheng-Wen Wu
A Low-Power CAM Design for LZ Data Compression. IEEE Trans. Computers 49(10): 1139-1145 (2000) - [j27]Kun-Jin Lin, Cheng-Wen Wu
Testing content-addressable memories using functional fault modelsand march-like algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 577-588 (2000) - [j26]Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
A fast signature computation algorithm for LFSR and MISR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1031-1040 (2000) - [j25]Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 503-516 (2000) - [j24]Chi-Feng Wu, Cheng-Wen Wu
Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI Design 10(3): 321-333 (2000) - [c29]Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12 - [c28]Jin-Hua Hong, Cheng-Wen Wu
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. ASP-DAC 2000: 565-570 - [c27]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50 - [c26]Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57 - [c25]Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min:
A waveform simulator based on Boolean process. Asian Test Symposium 2000: 145-150 - [c24]Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu:
A Testable/Fault Tolerant FFT Processor Design. Asian Test Symposium 2000: 429- - [c23]Juin-Ming Lu, Cheng-Wen Wu
Cost and Benefit Models for Logic and Memory BIST. DATE 2000: 710-714 - [c22]Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299- - [c21]Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471 - [c20]Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
Built-in self-test and fault diagnosis for lookup table FPGAs. ISCAS 2000: 80-83 - [c19]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS 2000: 291-296
1990 – 1999
- 1999
- [j23]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16(1): 59-70 (1999) - [j22]Wen-Feng Chang, Cheng-Wen Wu:
TSC Berger-Code Checker Design for 2r-1-Bit Information. J. Inf. Sci. Eng. 15(3): 429-440 (1999) - [j21]Shih-Arn Hwang, Cheng-Wen Wu:
Test Energy Minimization for C-Testable ILAs. J. Inf. Sci. Eng. 15(6): 899-911 (1999) - [j20]Wen-Feng Chang, Cheng-Wen Wu
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. IEEE Trans. Computers 48(8): 815-826 (1999) - [j19]Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 280-284 (1999) - [c18]Chi-Feng Wu, Cheng-Wen Wu
Testing Interconnects of Dynamic Reconfigurable FPGAs. ASP-DAC 1999: 279-282 - [c17]Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu:
Defect Level Prediction Using Multi-Model Fault Coverage. Asian Test Symposium 1999: 301- - [c16]Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES: A Fast Memory Fault Simulator. DFT 1999: 165-173 - [c15]Jin-Fu Li, Cheng-Wen Wu
Testable and Fault Tolerant Design for FFT Networks. DFT 1999: 201-209 - [c14]Shyue-Kung Lu, Cheng-Wen Wu:
A novel approach to testing LUT-based FPGAs. ISCAS (1) 1999: 173-177 - 1998
- [j18]Yeong-Ruey Shieh, Cheng-Wen Wu
Control and Observation Structures for Analog Circuits. IEEE Des. Test Comput. 15(2): 56-64 (1998) - [j17]Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu
Sequential circuit fault simulation using logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 724-736 (1998) - [j16]Yeong-Ruey Shieh, Cheng-Wen Wu
Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. VLSI Design 5(4): 357-372 (1998) - [c13]Cheng-Wen Wu, Chih-Yuang Su:
A Probabilistic Model for Path Delay Faults. Asian Test Symposium 1998: 70-75 - [c12]Yu-Chun Chuang, Cheng-Wen Wu:
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. Asian Test Symposium 1998: 301-305 - [c11]Cheng-Wen Wu
Testing Embedded Memories: Is BIST the Ultimate Solution? Asian Test Symposium 1998: 516-517 - 1997
- [j15]Kun-Jin Lin, Cheng-Wen Wu
Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications. J. Circuits Syst. Comput. 7(1): 31-48 (1997) - [j14]Wen-Feng Chang, Cheng-Wen Wu:
Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates? J. Inf. Sci. Eng. 13(4): 681-695 (1997) - [j13]Shyue-Kung Lu, Sy-Yen Kuo
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. IEEE Trans. Computers 46(9): 1028-1034 (1997) - [c10]Cheng-Wen Wu:
On energy efficiency of VLSI testing. Asian Test Symposium 1997: 132-137 - [c9]Chih-Tsun Huang, Cheng-Wen Wu:
High-speed C-testable systolic array design for Galois-field inversion. ED&TC 1997: 342-346 - 1996
- [j12]Shyue-Kung Lu, Cheng-Wen Wu
Cell delay fault testing for iterative logic arrays. J. Electron. Test. 9(3): 311-316 (1996) - [c8]Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. Asian Test Symposium 1996: 50-55 - [c7]Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu:
A MISR Computation Algorithm for Fast Signature Simulation. Asian Test Symposium 1996: 213-218 - 1995
- [j11]Yih-Lang Li, Cheng-Wen Wu
Cellular automata for efficient parallel logic and fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 740-749 (1995) - [j10]Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
C-testable design techniques for iterative logic arrays. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 146-152 (1995) - [j9]Cheng-Wen Wu
Bit-level systolic arrays for finite-field multiplications. J. VLSI Signal Process. 10(1): 85-92 (1995) - [c6]Yeong-Ruey Shieh, Cheng-Wen Wu:
DC control and observation structures for analog circuits. Asian Test Symposium 1995: 120-126 - 1994
- [j8]Shih-Yuang Su, Cheng-Wen Wu
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. IEEE Trans. Computers 43(4): 495-501 (1994) - [c5]Yih-Lang Li, Cheng-Wen Wu:
Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC 1994: 552-556 - [c4]Cheng-Wen Wu, Yung-Fa Chou:
General Modular Multiplication by Block Multiplication and Table Lookup. ISCAS 1994: 295-298 - 1993
- [j7]Cheng-Wen Wu, Jiann-Yuan Choue:
Fault-Tolerant FFT Butterfly Network Design. J. Inf. Sci. Eng. 9(1): 137-150 (1993) - 1991
- [j6]Kun-Jin Lin, Cheng-Wen Wu:
Easily Testable Cellular Array Multipliers. J. Inf. Sci. Eng. 7(3): 367-383 (1991) - [j5]Cheng-Wen Wu
Bit-level pipelined 2-D digital filters for real-time image processing. IEEE Trans. Circuits Syst. Video Technol. 1(1): 22-34 (1991) - [c3]Cheng-Wen Wu, Shyue-Kung Lu:
Designing Self-Testable Cellular Arrays. ICCD 1991: 110-113 - 1990
- [j4]Cheng-Wen Wu:
Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays. J. Inf. Sci. Eng. 6(1): 63-72 (1990) - [j3]Cheng-Wen Wu
Easily Testable Iterative Logic Arrays. IEEE Trans. Computers 39(5): 640-652 (1990)
1980 – 1989
- 1988
- [j2]Cheng-Wen Wu
Application-specific CAD of VLSI second-order sections. IEEE Trans. Acoust. Speech Signal Process. 36(5): 813-825 (1988) - 1987
- [j1]Peter R. Cappello, Cheng-Wen Wu
Computer-aided design of VLSI FIR filters. Proc. IEEE 75(9): 1260-1271 (1987) - [c2]Cheng-Wen Wu, Peter R. Cappello:
Application-Specific CAD of High-Throughout IIR Filters. COMPCON 1987: 302-305 - [c1]Cheng-Wen Wu, Peter R. Cappello:
Computer-aided design of VLSI second-order sections. ICASSP 1987: 1907-1910
Coauthor Index
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