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Chewnpu Jou
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2020 – today
- 2024
- [c23]Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS 2024: 85-89 - 2022
- [c22]Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu:
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS 2022: 46-49
2010 – 2019
- 2019
- [j5]Yanghyo Kim
, Boyu Hu, Yuan Du
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. IEEE J. Solid State Circuits 54(6): 1600-1612 (2019) - [j4]Kai Xu
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54(7): 2028-2037 (2019) - [c21]Feng-Wei Kuo, Zhirui Zong
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - 2018
- [j3]Feng-Wei Kuo
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3756-3768 (2018) - [c20]Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. ISSCC 2018: 278-280 - 2017
- [j2]Feng-Wei Kuo
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52(4): 1144-1162 (2017) - 2016
- [j1]Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51(7): 1547-1565 (2016) - [c19]Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC 2016: 36-37 - [c18]Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC 2016: 184-185 - [c17]Feng-Wei Kuo, Sandro Binsfeld Ferreira
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits 2016: 1-2 - 2015
- [c16]Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu:
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. 3DIC 2015: TS6.3.1-TS6.3.4 - [c15]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC 2015: 356-359 - [c14]Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC 2015: 1-3 - 2014
- [c13]Li-Wei Chu, Chun-Yu Lin
ESD protection design for wideband RF applications in 65-nm CMOS process. ISCAS 2014: 1480-1483 - [c12]Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC 2014: 1-2 - 2013
- [c11]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c10]I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh:
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC 2013: 414-415 - 2012
- [c9]Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. CICC 2012: 1-4 - [c8]Li-Wei Chu, Chun-Yu Lin
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. ISCAS 2012: 2127-2130 - [c7]Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. ISSCC 2012: 50-52 - [c6]Miki Moyal, Chewnpu Jou:
Session 24 overview: 10GBase-T and optical front ends: Wireline subcommittee. ISSCC 2012: 408-409 - 2011
- [c5]Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. ISSCC 2011: 488-490 - 2010
- [c4]W. M. Young, Chua-Huang Huang, Alan P. Su, Chewnpu Jou, Fu-Lung Hsueh:
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. ASP-DAC 2010: 821-824 - [c3]Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai:
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS. CICC 2010: 1-4 - [c2]Zhiwei Xu, Qun Jane Gu, Yi-Cheng Wu, Adrian Tang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang
D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link. CICC 2010: 1-4 - [c1]David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX. ESSCIRC 2010: 258-261
Coauthor Index
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