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ASP-DAC 2012: Sydney, Australia
- Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. IEEE 2012, ISBN 978-1-4673-0770-3
- Giovanni De Micheli:
Engineering complex systems for health, security and the environment. 1-6 - Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
:
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. 7-16 - Muhammad Nadeem
JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency. 17-22 - Marisha Rawlins, Ann Gordon-Ross:
An application classification guided cache tuning heuristic for multi-core architectures. 23-28 - Leandro Fiorin, Alberto Ferrante
Security Enhanced Linux on embedded systems: A hardware-accelerated implementation. 29-34 - Wei-Che Tseng, Chun Jason Xue
PRR: A low-overhead cache replacement algorithm for embedded processors. 35-40 - Baktash Boghrati, Sachin S. Sapatnekar
Incremental power network analysis using backward random walks. 41-46 - Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie:
Thermal-aware power network design for IR drop reduction in 3D ICs. 47-52 - Nauman H. Khan, Soha Hassoun:
The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits. 53-58 - Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao:
An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. 59-65 - Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho
An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips. 67-72 - Yi-Chung Chen, Wei Zhang
A Look Up Table design with 3D bipolar RRAMs. 73-78 - Dimin Niu, Yang Xiao, Yuan Xie:
Low power memristor-based ReRAM design with Error Correcting Code. 79-84 - Mathias Soeken
Synthesis of reversible circuits with minimal lines for large functions. 85-92 - Mike O'Connor
Accelerated processing and the Fusion System Architecture. 93 - Alex A. T. Bui, Kwang-Ting Cheng
Platform characterization for Domain-Specific Computing. 94-99 - Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson
GreenDroid: An architecture for the Dark Silicon Age. 100-105 - Ravi R. Iyer:
Accelerator-rich architectures: Implications, opportunities and challenges. 106-107 - Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan:
A reconfigurable platform for the design and verification of domain-specific accelerators. 108-113 - Rong Ye, Qiang Xu
Learning-based power management for multi-core processors via idle period manipulation. 115-120 - Ye-Jyun Lin, Chia-Lin Yang
Memory access aware power gating for MPSoCs. 121-126 - Yuankai Chen, Hai Zhou:
Buffer minimization in pipelined SDF scheduling on multi-core platforms. 127-132 - Shuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He, Pei Zhang, Huazhong Yang:
A hierarchical C2RTL framework for FIFO-connected stream applications. 133-138 - Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen:
Escape routing of differential pairs considering length matching. 139-144 - Yukihide Kohira, Atsushi Takahashi
An any-angle routing method using quasi-Newton method. 145-150 - Tao Lin, Sheqin Dong, Song Chen
Linear optimal one-sided single-detour algorithm for untangling twisted bus. 151-156 - Hailong Yao, Yici Cai, Qiang Gao:
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. 157-162 - Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra:
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. 163-168 - Yubin Zhang, Haile Yu, Qiang Xu
CODA: A concurrent online delay measurement architecture for critical paths. 169-174 - Mohammad Abdur Rouf, Soontae Kim:
Low-cost control flow error protection by exploiting available redundancies in the pipeline. 175-180 - Alexandru Paler, Ilia Polian, John P. Hayes:
Detection and diagnosis of faulty quantum circuits. 181-186 - Sascha Roloff, Frank Hannig
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. 187-192 - Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe:
Invasive manycore architectures. 193-200 - Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May:
Hardware prototyping of novel invasive multicore architectures. 201-206 - Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour
Invasive Computing for robotic vision. 207-212 - Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi:
Abstract system-level models for early performance and power exploration. 213-218 - Wolfgang Müller, Markus Becker, Ahmed Elfeky, Anthony DiPasquale:
Virtual prototyping of Cyber-Physical Systems. 219-226 - Rainer Dömer, Weiwei Chen, Xu Han:
Parallel discrete event simulation of Transaction Level Models. 227-231 - Masahiro Fujita, Hiroaki Yoshida:
Post-silicon patching for verification/debugging with high-level models and programmable logic. 232-237 - Keisuke Inoue, Mineo Kaneko:
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. 239-244 - Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. 245-250 - Yuko Hara, Hiroyuki Tomiyama:
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis. 251-256 - Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong:
An integrated and automated memory optimization flow for FPGA behavioral synthesis. 257-262 - Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan:
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. 263-270 - Saket Gupta, Sachin S. Sapatnekar
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. 271-276 - Kwanyeob Chae, Saibal Mukhopadhyay:
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs. 277-282 - Shuta Kimura, Masanori Hashimoto
Body bias clustering for low test-cost post-silicon tuning. 283-289 - Subhasish Mitra, David Lin, Nagib Hakim, Donald S. Gardner:
Bug localization techniques for effective post-silicon validation. 291 - Peter Lisherness, Kwang-Ting Cheng
Improving validation coverage metrics to account for limited observability. 292-297 - Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita:
Automated data analysis techniques for a modern silicon debug environment. 298-303 - Amir Nahir, Avi Ziv, Subrat Panda:
Optimizing test-generation to the execution platform. 304-309 - Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan:
When to forget: A system-level perspective on STT-RAMs. 311-316 - Tianzheng Wang, Duo Liu, Zili Shao
Write-activity-aware page table management for PCM-based embedded systems. 317-322 - Yiran Chen, Yaojun Zhang, Peiyuan Wang:
Probabilistic design in spintronic memory and logic circuit. 323-328 - Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi
Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. 329-334 - Dae Hyun Kim, Rasit Onur Topaloglu
Block-level 3D IC design with through-silicon-via planning. 335-340 - Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen:
Micro-bump assignment for 3D ICs using order relation. 341-346 - Xin Zhao, Sung Kyu Lim
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. 347-352 - Lijuan Luo, Martin D. F. Wong
Parallel implementation of R-trees on the GPU. 353-358 - Xiaoming Chen, Yu Wang
An adaptive LU factorization algorithm for parallel circuit simulation. 359-364 - Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai
Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. 365-370 - Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Crosstalk-aware statistical interconnect delay calculation. 371-376 - Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye:
Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functions. 377-382 - Yen-Kuang Chen
Challenges and opportunities of internet of things. 383-388 - Wei Liu, Xiaotian Fei, Tao Tang, Pengjun Wang, Hong Luo, Beixing Deng, Huazhong Yang:
Application specific sensor node architecture optimization - Experiences from field deployments. 389-394 - Shih-Hao Hung
System-wide profiling and optimization with virtual machines. 395-400 - Shao-Yi Chien
Power optimization of wireless video sensor nodes in M2M networks. 401-405 - Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. 407-412 - Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila
ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures. 413-418 - Jinho Lee
Memory-aware mapping and scheduling of tasks and communications on many-core SoC. 419-424 - Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen:
A fast thermal aware placement with accurate thermal analysis based on Green function. 425-430 - Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin
Crosstalk-aware power optimization with multi-bit flip-flops. 431-436 - Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li:
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. 437-442 - Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu:
Voltage island-driven floorplanning considering level shifter placement. 443-448 - Dukyoung Yun, Sungchan Kim, Soonhoi Ha:
Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems. 449-454 - Rohit Sinha, Aayush Prakash, Hiren D. Patel:
Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs. 455-460 - Weiwei Chen, Rainer Dömer:
An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation. 461-466 - Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada
A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. 467-468 - Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. 469-470 - Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura:
CMA-2 : The second prototype of a low power reconfigurable accelerator. 471-472 - Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh:
Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. 473-474 - Shoun Matsunaga, Masanori Natsui
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. 475-476 - Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu:
Energy-efficient RISC design with on-demand circuit-level timing speculation. 477-478 - Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng:
A 60mW baseband SoC for CMMB receiver. 479-480 - Chongmin Li, Dongsheng Wang, Haixia Wang, Yibo Xue, Jian Li:
Proximity-Aware cache Replication. 481-486 - Jinglei Wang, Dongsheng Wang, Haixia Wang, Yibo Xue:
Dynamic reusability-based replication with network address mapping in CMPs. 487-492 - Ke Yue, Frank Lockom, Zheng Li, Soumia Ghalim, Shangping Ren, Lei Zhang, Xiaowei Li:
Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC. 493-498 - Hany Kashif, Hiren D. Patel, Sebastian Fischmeister:
Using link-level latency analysis for path selection for real-time communication on NoCs. 499-504 - Shihheng Tsai, Man-Yu Li, Chung-Yang Huang:
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. 505-510 - Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. 511-516 - Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang:
Clock rescheduling for timing engineering change orders. 517-522 - Li Li, Yinghai Lu, Hai Zhou:
Optimal prescribed-domain clock skew scheduling. 523-527 - Yang Shang, Wei Fei, Hao Yu:
Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables. 529-534 - Xuexin Liu, Sheldon X.-D. Tan, Zhigang Hao, Guoyong Shi:
Time-domain performance bound analysis of analog circuits considering process variations. 535-540 - Yang Song, Guoyong Shi:
Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties. 541-546 - Tingting Wang, Haotian Liu, Yuanzhe Wang, Ngai Wong:
Weakly nonlinear circuit analysis based on fast multidimensional inverse Laplace transform. 547-552 - Kiichi Niitsu
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. 553-554 - Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda:
Simultaneous data and power transmission using nested clover coils. 555-556 - Ya-Ting Chang, Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu:
Complexity-effective auditory compensation with a controllable filter for digital hearing aids. 557-558 - Ahmed Musa, Kenichi Okada
A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. 559-560 - Takeshi Kuboki
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. 561-562 - Wei Deng, Kenichi Okada
A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. 563-564 - Dan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiaoyang Zeng:
A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS. 565-566 - Parisa Razaghi, Andreas Gerstlauer:
Automatic timing granularity adjustment for host-compiled software simulation. 567-572 - Marco Lattuada
Performance estimation of embedded software with confidence levels. 573-578 - Jayanand Asok Kumar, Shobha Vasudevan:
Verifying dynamic power management schemes using statistical model checking. 579-584 - Aritra Hazra, Pallab Dasgupta, Ansuman Banerjee, Kevin Harer:
Formal methods for coverage analysis of architectural power states in power-managed designs. 585-590 - Jianxin Fang, Sachin S. Sapatnekar
The impact of hot carriers on timing in large circuits. 591-596 - Da-Cheng Juan, Huapeng Zhou, Diana Marculescu
A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors. 597-602 - Pei-Yu Huang, Yu-Min Lee, Chi-Wen Pan:
On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques. 603-608 - Michael B. Henry, Leyla Nazhandali:
Design techniques for functional-unit power gating in the Ultra-Low-Voltage region. 609-614 - Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems. 615-620 - Duo Ding, Bei Yu, David Z. Pan:
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. 621-626 - Qing Xie, Yanzhi Wang, Massoud Pedram, Younghyun Kim
Charge replacement in hybrid electrical energy storage systems. 627-632 - Borislav Alexandrov, Owen Sullivan, Satish Kumar, Saibal Mukhopadhyay:
Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors. 633-638 - Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing. 639 - Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi:
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. 640-645 - Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang:
Post silicon skew tuning: Survey and analysis. 646-651 - Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza:
Compilation and architecture support for customized vector instruction extension. 652-657 - Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Thread affinity mapping for irregular data access on shared Cache GPGPU. 659-664 - Martin Lukasiewycz, Reinhard Schneider, Dip Goswami, Samarjit Chakraborty
Modular scheduling of distributed heterogeneous time-triggered automotive systems. 665-670 - Semeen Rehman, Muhammad Shafique
RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware. 671-676 - Huang Huang, Ming Fan, Gang Quan
On-line leakage-aware energy minimization scheduling for hard real-time systems. 677-682 - Bijan Alizadeh:
A formal approach to debug polynomial datapath designs. 683-688 - Miroslav N. Velev
Automated debugging of counterexamples in formal verification of pipelined microprocessors. 689-694 - Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita:
On error tolerance and Engineering Change with Partially Programmable Circuits. 695-700 - Ming Gao, Peter Lisherness, Kwang-Ting Cheng
On error modeling of electrical bugs for post-silicon timing validation. 701-706 - Yuelin Du, Hongbo Zhang, Martin D. F. Wong
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. 707-712 - Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Design-patterning co-optimization of SRAM robustness for double patterning lithography. 713-718 - Hongbo Zhang, Yuelin Du, Martin D. F. Wong
Efficient pattern relocation for EUV blank defect mitigation. 719-724 - Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham:
Character design and stamp algorithms for Character Projection Electron-Beam Lithography. 725-730 - Qiang Xu
Yield enhancement for 3D-stacked ICs: Recent advances and challenges. 731-737 - Jing Xie, Yu Wang, Yuan Xie:
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs. 738-743 - Cheng-Wen Wu
On test and repair of 3D random access memory. 744-749 - David Z. Pan, Sung Kyu Lim
Design for manufacturability and reliability for TSV-based 3D ICs. 750-755 - Peng Li, Weikang Qian, Marc D. Riedel
The synthesis of linear Finite State Machine-based Stochastic Computational Elements. 757-762 - Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Selective time borrowing for DSP pipelines with hybrid voltage control loop. 763-768 - Yavuz Yetim, Sharad Malik
EPROF: An energy/performance/reliability optimization framework for streaming applications. 769-774 - Saket Gupta, Sachin S. Sapatnekar
BTI-aware design using variable latency units. 775-780 - Tsutomu Sasao:
Linear decomposition of index generation functions. 781-788 - Omid Sarbishei, Katarzyna Radecka:
Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. 789-794 - Kiyoung Kim, Taewhan Kim:
Algorithm for synthesizing design context-aware fast carry-skip adders. 795-800 - Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng:
A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder. 801-806 - Xiang Chen, Jian Zheng, Yiran Chen, Wei Zhang
Fine-grained dynamic voltage scaling on OLED display. 807-812 - Jagdish Sabarad, Srinidhi Kestur, Mi Sun Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla:
A reconfigurable accelerator for neuromorphic object recognition. 813-818 - Héctor Pettenghi
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. 819-824
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