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ETS 2013: Avignon, France
- 18th IEEE European Test Symposium, ETS 2013, Avignon, France, May 27-30, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6376-1
- Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka:
A minimum MSE sensor fusion algorithm with tolerance to multiple faults. 1 - Martin Omaña, Daniele Rossi
, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache:
Novel approach to reduce power droop during scan-based logic BIST. 1-6 - Shyam Kumar Devarakond, Debashis Banerjee, Aritra Banerjee, Shreyas Sen, Abhijit Chatterjee:
Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters. 1-6 - Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor:
Bias temperature instability analysis in SRAM decoder. 1 - Elena I. Vatajelu
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. 1-6 - Christophe Kelma, Sébastien Darfeuille, Andreas Neuburger, Andreas Lobnig:
RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology. 1 - Afsaneh Nassery, Sule Ozev, Mustapha Slamani:
Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion. 1-6 - Daniel Arumí
BIST architecture to detect defects in tsvs during pre-bond testing. 1 - Panagiota Papavramidou, Michael Nicolaidis:
Reducing power dissipation in memory repair for high defect densities. 1-7 - Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Scan pattern retargeting and merging with reduced access time. 1-7 - Hans A. R. Manhaeve, Esko Mikkola:
Semiconductor failure modes and mitigation for critical systems embedded tutorial. 1-3 - Jeremy Dubeuf, David Hély
Run-time detection of hardware Trojans: The processor protection unit. 1-6 - Samuel Evain, Valentin Gherman:
Error-correction schemes with erasure information for fast memories. 1-6 - Manuel J. Barragan Asian, Gildas Léger
Efficient selection of signatures for analog/RF alternate test. 1-6 - Yuxi Liu, Rong Ye, Feng Yuan, Qiang Xu
Optimization for timing-speculated circuits by redundancy addition and removal. 1-6 - Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. 1 - Unni Chandran, Dan Zhao, Rathish Jayabharathi:
Hybrid 3D pre-bonding test framework design. 1 - Mohand Bentobache
Efficient minimization of test frequencies for linear analog circuits. 1 - Irith Pomeranz:
Generation of compact multi-cycle diagnostic test sets. 1 - Matteo Sonza Reorda
An error-detection and self-repairing method for dynamically and partially reconfigurable systems. 1-7 - Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello
Current testing: Dead or alive? 1 - Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. 1 - Giuseppe Di Guglielmo, Davide Ferraretto, Franco Fummi, Graziano Pravadelli
Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software. 1-6 - Haithem Ayari, Florence Azaïs, Serge Bernard
Implementing model redundancy in predictive alternate test to improve test confidence. 1 - Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
New test compression scheme based on low power BIST. 1-6 - Stefano Di Carlo
A software-based self test of CUDA Fermi GPUs. 1-6 - Said Hamdioui, Davide Appello
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes? 1 - Carolina Metzler, Aida Todri-Sanial
Computing detection probability of delay defects in signal line tsvs. 1-6 - Paolo Rech
Experimental evaluation of thread distribution effects on multiple output errors in GPUs. 1-6 - Ozgur Sinanoglu
Reconciling the IC test and security dichotomy. 1-6 - Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
M-S test based on specification validation using octrees in the measure space. 1-6 - Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang:
Utilizing circuit structure for scan chain diagnosis. 1-6 - Jeff Rearick:
Magical thinking applied to test engineering reality (and vice versa). 1 - Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
Test generation for circuits with embedded memories using SMT. 1 - Sergej Deutsch, Krishnendu Chakrabarty
Robust optimization of test-architecture designs for core-based SoCs. 1-6 - Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Variability-aware and fault-tolerant self-adaptive applications for many-core chips. 1 - Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. 1-6 - Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori:
A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing. 1-6 - H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang:
A mutual characterization based SAR ADC self-testing technique. 1-6 - Nikil D. Dutt
Outlook for many-core systems: Cloudy with a chance of virtualization. 1 - Ke Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris
On combining alternate test with spatial correlation modeling in analog/RF ICs. 1-6 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis. 1-6 - Jie Han, Michael Orshansky:
Approximate computing: An emerging paradigm for energy-efficient design. 1-6 - Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
Adaptive quality binning for analog circuits. 1-6 - Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. 1-6
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