default search action
23. ACM Great Lakes Symposium on VLSI 2014: Houston, TX, USA
- Joseph R. Cavallaro, Tong Zhang, Alex K. Jones, Hai (Helen) Li:
Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. ACM 2014, ISBN 978-1-4503-2816-6
Keynote I
- Keshab K. Parhi
:
VLSI systems for neurocomputing and health informatics. 1-2
Reliability, resiliency, robustness I
- Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. 3-8 - Zheng Wang, Chao Chen, Piyush Sharma, Anupam Chattopadhyay:
System-level reliability exploration framework for heterogeneous MPSoC. 9-14 - Rickard Ewetz, Anirudh Udupa
A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness. 15-20 - Renyuan Zhang, Mineo Kaneko:
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism. 21-26
CAD
- Andrew B. Kahng, Hyein Lee, Jiajia Li:
Horizontal benchmark extension for improved assessment of physical CAD research. 27-32 - Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee
OCV-aware top-level clock tree optimization. 33-38 - Alessandro Sassone, Donghwa Shin, Alberto Bocca, Alberto Macii
Modeling of the charging behavior of li-ion batteries based on manufacturer's data. 39-44 - Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N.:
High level energy modeling of controller logic in data caches. 45-50
Best paper session
- Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie:
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. 51-56 - Andrew B. Kahng, Hyein Lee:
Minimum implant area-aware gate sizing and placement. 57-62 - Pham Nam Khanh, Amit Kumar Singh, Akash Kumar
A multi-stage leakage aware resource management technique for reconfigurable architectures. 63-68
Poster session 1
- Tuhin Subhra Das, Prasun Ghosal, Saraju P. Mohanty, Elias Kougianos:
A performance enhancing hybrid locally mesh globally star NoC topology. 69-70 - Dominik Auras, Dominik Rieth, Rainer Leupers, Gerd Ascheid:
VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract. 71-72 - Yue Fu, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram:
Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control. 73-74 - Jing Lu, Yong-Bin Kim:
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters. 75-76 - Simi Zerine Sleeba, John Jose
WeDBless: weighted deflection bufferless router for mesh NoCs. 77-78 - Wenchao Qian, Robert Karam, Swarup Bhunia
Trade-off between energy and quality of service through dynamic operand truncation and fusion. 79-80 - Zhuo Qian, Martin Margala
A novel low-power and in-place split-radix FFT processor. 81-82 - Fábio I. Pereira, André Borin Soarez, Altamiro Amadeu Susin, Alexsandro Cristovão Bonatto
H.264 8x8 inverse transform architecture optimization. 83-84 - Md Shahriar Shamim, Naseef Mansoor, Aman Samaiyar, Amlan Ganguly, Sujay Deb
Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas. 85-86 - Michael Gautschi, Davide Rossi
Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory. 87-88 - Michael J. Hall, Roger D. Chamberlain:
Performance modeling of virtualized custom logic computations. 89-90 - Mineo Kaneko:
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]. 91-92 - Ho Joon Lee, Yong-Bin Kim:
An area efficient low power high speed S-Box implementation using power-gated PLA. 93-94 - Hocine Merabti, Daniel Massicotte:
FPGA based implementation of a genetic algorithm for ARMA model parameters identification. 95-96 - Manoj Kumar
Highly adaptive and congestion-aware routing for 3D NoCs. 97-98
Energy efficient systems
- Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, Spyros Tragoudas:
Adaptive compressive sensing for low power wireless sensors. 99-104 - Selçuk Köse
Regulator-gating: adaptive management of on-chip voltage regulators. 105-110 - Ta-Kai Lin, Kuen-Wey Lin
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. 111-116
Design methodology
- Mohammad Javad Dousti, Alireza Shafaei, Massoud Pedram:
Squash: a scalable quantum mapper considering ancilla sharing. 117-122 - Kenneth Ramclam, Swaroop Ghosh:
Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory. 123-128 - Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. 129-134
Gala dinner keynote
- Gene A. Frantz:
Create, then innovate. 135-136
Keynote II
- Edgar Sánchez-Sinencio:
Smart nodes of internet of things (IoT): a hardware perspective view & implementation. 137-138
Reliability, resiliency, robustness II
- Sparsh Mittal
WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling. 139-144 - Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu
Reliability-aware cross-point resistive memory design. 145-150 - Nikolaos Papandreou, Thomas P. Parnell, Haralampos Pozidis, Thomas Mittelholzer, Evangelos Eleftheriou, Charles Camp, Thomas Griffin, Gary A. Tressler, Andrew Walls:
Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems. 151-156 - Andrew B. Kahng, Seokhyeong Kang, Jiajia Li:
A new methodology for reduced cost of resilience. 157-162
Application specific designs
- Yi Xiang, Sudeep Pasricha:
A hybrid framework for application allocation and scheduling in multicore systems with energy harvesting. 163-168 - Schuyler Eldridge
Neural network-based accelerators for transcendental function approximation. 169-174 - Pirmin Vogel, Andrea Bartolini
Efficient parallel beamforming for 3D ultrasound imaging. 175-180 - Yang Xiao, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan, Chuanjun Zhang:
A task-oriented vision system. 181-186
Memory designs
- Yoshiro Riho, Kazuo Nakazato:
A new DRAM architecture and its control method for the system power consumption. 187-192 - Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy:
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. 193-198 - Wei Wei, Kazuteru Namba, Fabrizio Lombardi:
New 4T-based DRAM cell designs. 199-204
Fault tolerance
- Chen Jiang, Mojing Liu, Brett H. Meyer:
MB-FICA: multi-bit fault injection and coverage analysis. 205-210 - Wei Song
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. 211-216 - Joseph Lenox, Spyros Tragoudas:
A novel parallel adaptation of an implicit path delay grading method. 217-222
Poster session 2
- Ebubechukwu Agu, Saraju P. Mohanty, Elias Kougianos, Mahesh Gautam:
Simscape design flow for memristor based programmable oscillators. 223-224 - Naval Gupte, Jia Wang:
Securely outsourcing power grid simulation on cloud. 225-226 - Thomas Peyret
An automated design approach to map applications on CGRAs. 229-230 - Francesco Conti
He-P2012: architectural heterogeneity exploration on a scalable many-core platform. 231-232 - Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu:
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. 233-234 - Pankaj Kumar, Pravin Neminath Kondekar, Sangeeta Singh:
Transient analysis of gate inside junctionless transistor (GI-JLT). 235-236 - Bo Yao, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen:
Built-in generation of functional broadside tests considering primary input constraints. 237-238 - Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie:
TSV power supply array electromigration lifetime analysis in 3D ICS. 239-240 - Cory E. Merkel, Dhireesha Kudithipudi:
A current-mode CMOS/memristor hybrid implementation of an extreme learning machine. 241-242 - Matthias Hartmann, Halil Kükner, Prashant Agrawal, Praveen Raghavan, Liesbet Van der Perre
Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories. 243-244 - Adriel Ziesemer, Ricardo Reis
A design flow for physical synthesis of digital cells with ASTRAN. 245-246 - Ons Lahiouel, Henda Aridhi, Mohamed H. Zaki
A semi-formal approach for analog circuits behavioral properties verification. 247-248
Reconfigurable components
- Adarsh Reddy Ashammagari, Hamid Mahmoodi
Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors. 249-254 - Gervin Thomas, Ahmed Elhossini, Ben H. H. Juurlink:
A generic implementation of a quantified predictor on FPGAs. 255-260 - Jing Yu, Paul Beckett:
A dual-rail LUT for reconfigurable logic using null convention logic. 261-266
System level optimization
- Marta Ortín-Obón
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. 267-272 - Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator. 273-278 - Tosiron Adegbija, Ann Gordon-Ross:
Thermal-aware phase-based tuning of embedded systems. 279-284
Keynote III
- Alex K. Jones:
EDA for extreme scale systems: design abstractions, metrics, and benchmarks. 285-286
Reconfigurable systems
- Sanchita Mal-Sarkar, Aswin Raghav Krishna, Anandaroop Ghosh, Swarup Bhunia
Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures. 287-292 - Christian Fobel, Gary William Grewal, Deborah Stacey
Forward-scaling, serially equivalent parallelism for FPGA placement. 293-298 - Amey M. Kulkarni, Houman Homayoun, Tinoosh Mohsenin:
A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction. 299-304
Analog design
- Paul Winkler, Henda Aridhi, Mohamed H. Zaki
Generation of reduced analog circuit models using transient simulation traces. 305-310 - Yongsuk Choi, Yong-Bin Kim:
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers. 311-316 - Ibtissem Seghaier, Henda Aridhi, Mohamed H. Zaki
A qualitative simulation approach for verifying PLL locking property. 317-322
Low power design
- Yanzhi Wang, Xue Lin, Massoud Pedram:
Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails. 323-328 - Zhufei Chu
Level shifter planning for timing constrained multi-voltage SoC floorplanning. 329-334 - Chen Liu, Chengmo Yang:
Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs. 335-340
Emerging technologies
- Retsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe:
Optically reconfigurable gate array with an angle-multiplexed holographic memory. 341-346 - Dhruva Ghai, Saraju P. Mohanty, Garima Thakral, Oghenekarho Okobiah:
Variability-aware design of double gate FinFET-based current mirrors. 347-352 - Monther Abusultan, Sunil P. Khatri:
A comparison of FinFET based FPGA LUT designs. 353-358
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 01:01 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: