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ISLPED 2006: Tegernsee, Bavaria, Germany
- Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu:
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006. ACM 2006, ISBN 1-59593-462-6
Keynote
- Christoph Kutter
:
Design challenges for mobile communication devices. 1
Emerging technologies and designs for low power
- Arijit Raychowdhury, Xuanyao Fong
Analysis of super cut-off transistors for ultralow power digital logic circuits. 2-7 - Joyce Kwong, Anantha P. Chandrakasan:
Variation-driven device sizing for minimum energy sub-threshold circuits. 8-13 - Ik Joon Chang, Jae-Joon Kim, Kaushik Roy:
Robust level converter design for sub-threshold logic. 14-19 - Nathaniel J. Guilar, Albert Chen, Travis Kleeburg, Rajeevan Amirtharajah
Integrated solar energy harvesting and storage. 20-24 - Samuel Rodríguez, Bruce L. Jacob:
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). 25-30
Microarchitectural techniques for low power
- Eric L. Hill, Mikko H. Lipasti:
Stall cycle redistribution in a transparent fetch pipeline. 31-36 - Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective writeback: exploiting transient values for energy-efficiency and performance. 37-42 - Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Energy-efficient dynamic instruction scheduling logic through instruction grouping. 43-48 - Grigorios Magklis, Pedro Chaparro, José González, Antonio González
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. 49-54 - Yongkang Zhu, David H. Albonesi:
Synergistic temperature and energy management in GALS processor architectures. 55-60
Circuit techniques for scaled technologies
- Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. 61-66 - Jonggab Kil, Jie Gu, Chris H. Kim:
A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. 67-72 - Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
A dual-VDD boosted pulsed bus technique for low power and low leakage operation. 73-78 - Keith A. Bowman
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. 79-84 - Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel:
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. 85-88
Power management and application specific architectures
- Wei-Chung Cheng, Chih-Fu Hsu, Chain-Fu Chao:
Temporal vision-guided energy minimization for portable displays. 89-94 - Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley
Dynamic current modeling at the instruction level. 95-100 - Hyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti:
Reducing idle mode power in software defined radio terminals. 101-106 - Maria G. Koziri, Georgios I. Stamoulis, Ioannis Katsavounidis:
Power reduction in an H.264 encoder through algorithmic and logic transformations. 107-112 - Girish Varatkar, Naresh R. Shanbhag:
Energy-efficient motion estimation using error-tolerance. 113-118
Low power circuits and microarchitectures
- Javid Jaffari, Mohab Anis:
Variability-aware device optimization under ION and leakage current constraints. 119-122 - Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi:
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. 123-126 - Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim:
Utilizing reverse short channel effect for optimal subthreshold circuit design. 127-130 - Jabulani Nyathi, Brent Bero:
Logic circuits operating in subthreshold voltages. 131-134 - Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. 135-138 - Shuo Wang, Lei Wang:
Thread-associative memory for multicore and multithreaded computing. 139-142 - Chung-Hsiang Lin, Chia-Lin Yang
Hierarchical value cache encoding for off-chip data bus. 143-146 - Lei Jin, Sangyeun Cho:
Reducing cache traffic and energy with macro data load. 147-150 - Axel Reimer, Arne Schulz, Wolfgang Nebel:
Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs. 151-154
Thermal and energy aware design
- Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. 156-161 - Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini
Dynamic thermal clock skew compensation using tunable delay buffers. 162-167 - Yan Lin, Yu Hu, Lei He, Vijay Raghunat:
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. 168-173 - Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing. 174-179
Energy management for sensor and memory systems
- Jason Hsu, Sadaf Zahedi, Aman Kansal, Mani B. Srivastava, Vijay Raghunathan:
Adaptive duty cycling for energy harvesting systems. 180-185 - Le Cai, Yung-Hsiang Lu:
Power reduction of multiple disks using dynamic cache resizing and speed control. 186-190 - Qinru Qiu, Qing Wu, Daniel J. Burns, Douglas Holzhauer:
Lifetime aware resource management for sensor network using distributed genetic algorithm. 191-196 - Farhan Simjee, Pai H. Chou:
Everlast: long-life, supercapacitor-operated wireless sensor node. 197-202
Embedded tutorial 1
- Sani R. Nassif:
Model to hardware matching: for nano-meter scale technologies. 203-206
Embedded tutorial 2
- Majid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Tammara Massey, Ani Nahapetian:
Low power light-weight embedded systems. 207-212
Keynote
- Barry Dennington:
Low power design from technology challenge to great products. 213
Leakage control and dynamic power optimization
- Baozhen Yu, Michael L. Bushnell:
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. 214-219 - Domenik Helms, Günter Ehmen, Wolfgang Nebel:
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. 220-225 - W. T. Cheung, N. Wong:
Power optimization in a repeater-inserted interconnect via geometric programming. 226-231 - Fei Hu, Vishwani D. Agrawal:
Input-specific dynamic power optimization for VLSI circuits. 232-237 - Yu Wang, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang:
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. 238-243
Memory hierarchy and caches
- Hui Zeng, Kanad Ghose:
Register file caching for energy efficiency. 244-249 - Elham Safi, Andreas Moshovos, Andreas G. Veneris:
L-CBF: a low-power, fast counting bloom filter architecture. 250-255 - Mohammad Sharifkhani, Manoj Sachdev:
A low power SRAM architecture based on segmented virtual grounding. 256-261 - Ke Meng, Russ Joseph:
Process variation aware cache leakage management. 262-267 - Alok Garg, Fernando Castro
Substituting associative load queue with simple hash tables in out-of-order microprocessors. 268-273
RF CMOS building blocks
- Amin Shameli, Payam Heydari:
A novel power optimization technique for ultra-low power RFICs. 274-279 - Alessio Facen, Andrea Boni:
A CMOS analog frontend for a passive UHF RFID tag. 280-285 - Stephan Henzler, Siegmar Koeppe:
High-speed low-power frequency divider with intrinsic phase rotator. 286-291
Temperature-aware design and microarchitectures
- Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang:
An optimal analytical solution for processor speed control with thermal constraints. 292-297 - Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. 298-303 - James Donald, Margaret Martonosi:
Power efficiency for variation-tolerant multicore processors. 304-309 - Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek:
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. 310-315 - Wonbok Lee, Kimish Patel, Massoud Pedram:
Dynamic thermal management for MPEG-2 decoding. 316-321
Low power mixed-signal and digital systems
- Song Guo, Hoi Lee:
A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCs. 322-325 - Changbo Long, Sasank Reddy, Sudhakar Pamarti
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. 326-329 - Anas A. Hamoui, T. Alhajj, Mohammad Taherzadeh-Sani
Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs. 330-333 - Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Low-power fanout optimization using MTCMOS and multi-Vt techniques. 334-337 - Scott Hanson, Dennis Sylvester, David T. Blaauw:
A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. 338-341 - Saumya Chandra, Kanishka Lahiri, Anand Raghunathan
Considering process variations during system-level power analysis. 342-345 - Mirko Loghi, Massimo Poncino, Luca Benini
Synchronization-driven dynamic speed scaling for MPSoCs. 346-349 - William Lloyd Bircher, Lizy K. John:
Power phase variation in a commercial server workload. 350-353 - Mahmut T. Kandemir, Seung Woo Son:
Reducing power through compiler-directed barrier synchronization elimination. 354-357 - Hakduran Koc, Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, Ehat Ercanli:
Minimizing energy consumption of banked memories using data recomputation. 358-362
Embedded tutorial 3
- Scott Hanson, Bo Zhai, David T. Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang:
Energy optimality and variability in subthreshold design. 363-365 - Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha P. Chandrakasan:
Sub-threshold design: the challenges of minimizing circuit energy. 366-368
Embedded tutorial 4
- Vijay Raghunathan, Pai H. Chou:
Design and power management of energy harvesting embedded systems. 369-374
Flexibility and Low Power: A Contradiction in Terms?
- Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson:
Flexibility and low power: a contradiction in terms? 375
Low power, low voltage circuits and DC/DC converters
- Malav Shah:
Efficient scan-based BIST scheme for low power testing of VLSI chips. 376-381 - Jie Gu, John Keane, Chris H. Kim:
Modeling and analysis of leakage induced damping effect in low voltage LSIs. 382-387 - Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen
Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC converters. 388-393 - Dongsheng Ma, Janet Meiling Wang, Pablo Vazquas:
Adaptive on-chip power supply with robust one-cycle control technique. 394-399 - Dongsheng Ma:
Robust multiple-phase switched-capacitor DC-DC converter with digital interleaving regulation scheme. 400-405
Low power architectures and systems
- Jie Jin, Chi-Ying Tsui
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. 406-411 - Feng Chen, Song Jiang, Xiaodong Zhang:
SmartSaver: turning flash drive into a disk energy saver for mobile computers. 412-417 - Hung-Wei Tseng
An energy-efficient virtual memory system with flash memory as the secondary storage. 418-423 - Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula:
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. 424-429
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