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ISQED 2000: San Jose, California, USA
- 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA. IEEE Computer Society 2000, ISBN 0-7695-0525-2
Evening Panel Discussion
- Robert N. Blair, Jacques Benkoski:
How Do You Select A High Quality EDA Tool Flow?. 17-
Plenary Session
- Aart J. de Geus:
Slap it Together and Ship it! 23-24 - John East:
The Practical Side of Quality. 25-26 - Prakash Agrawal:
Design for Quality and Manufacturing. 27-28 - John Kibarian:
Ramping New IC Products in the Deep Submicron Age. 29-
Panel Discussion
- Michael Reinhardt, Michael Santarini:
What is Design Quality? How can Quality in Electronic Design be Quantified? 31-
DSM Modeling
- Michael S. Shur
, Tor A. Fjeldly, Trond Ytterdal:
Transistor Modeling for the VDSM Era. 37-44 - Gilbert Yoh, Farid N. Najm:
A Statistical Model for Electromigration Failures. 45-50 - Murat R. Becer, Ibrahim N. Hajj:
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. 51-58 - Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino:
Power Macromodeling for a High Quality RT-Level Power Estimation. 59-
Emerging Process and Device Technology
- Jiann-Shiun Yuan:
Overview of SiGe Technology Modeling and Application. 67-72 - Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami:
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. 73-80 - Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo:
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC. 81-86 - Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim:
Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's. 87-
Quality of Design and EDA Tools
- Lech Józwiak:
Quality-Driven System-on-a-Chip Design. 93- - Giora Ben-Yaacov, Larry Bjork, Edward P. Stone:
Advancing Customer-Perceived Quality in the EDA Industry. 411- - Betty Prince:
Quality Memory Blocks -- Balancing the Trade-Offs. 109-114 - Israel Koren:
Should Yield be a Design Objective? 115-120 - Anna Fontanelli, Luigi Arnone, Roberto Branca, Giorgio Mastrorocco:
Early Addressing IC and Package Relationship Allows an Overall Better Quality of Complex SOC. 121-
Emerging Integrity Issues
- Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano:
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. 129-136 - Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Dynamic Timing Analysis Considering Power Supply Noise Effects. 137-144 - Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie:
Full Chip Thermal Simulation. 145-150 - Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant:
Enabling DIR(Designing-In-Reliability) through CAD Capabilities. 151-156 - Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Noise Safety Design Methodologies. 157-
Low Power Test
- Thomas W. Williams, Rohit Kapur:
Design for Testability in Nanometer Technologies; Searching for Quality. 167-172 - Patrick Girard:
Low Power Testing of VLSI Circuits: Problems and Solutions. 173-180 - Zhanping Chen, Liqiong Wei, Kaushik Roy:
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. 181-188 - Raimund Ubar, Jaan Raik
Efficient Hierarchical Approach to Test Generation for Digital Systems. 189-196 - Octávio Páscoa Dias, Jorge Semião
Quality of Electronic Design: From Architectural Level to Test Coverage. 197-
Evening Panel Discussion
- Richard Goering, Richard Wallace:
The Hidden Costs of Design Qualit. 203-
Plenary Session
- Alberto L. Sangiovanni-Vincentelli:
Platform-Based Design: A Path to Efficient Design Re-Use. 209-210 - Yervant Zorian:
Embedded-Quality for Test. 211-212 - Kamran Eshraghian:
Deep Submicron USLI Design Paradigm: Who is Writing the Future? 213-
Quality of IP Blocks
- Tomás Bautista
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells. 217-226 - Dave Protheroe, Francesco Pessolano:
An Objective Measure of Digital System Design Quality. 227-233 - Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson
Achieving the Quality of Verification for Behavioral Models with Minimum Effort. 234-
Impact of Emerging Processes on Design Quality
- Ashok K. Sinha:
Extending Moore's Law through Advances in Semiconductor Manufacturing Equipment. 243-244 - Ana Hunter, C. K. Lau, John Martin:
Combining Advanced Process Technology and Design for Systems Level Integration. 245-250 - Charvaka Duvvury:
ESD: Design For IC Chip Quality and Reliability. 251-
Poster Session
- Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 263-268 - Mely Chen Chi, Shih-Hsu Huang:
A Reliable Clock Tree Design Methodology for ASIC Designs. 269-274 - Peter H. Chen, Sunil Malkani, Chun-Mou Peng, James Lin:
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion. 275-282 - Donald J. Dent:
Project Management for System-on-Chip Using Multi-Chip Modules. 283-290 - Mohamed Dessouky, Marie-Minerve Louërat:
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. 291-298 - Th. Haniotakis, Y. Tsiatouhas
On Testability of Multiple Precharged Domino Logic. 299-304 - Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada:
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. 305-308 - J. L. Knighten, N. W. Smith, L. O. Hoeft, J. T. DiBene II:
EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates. 309-314 - Wieslaw Kuzmicz
Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs. 315-320 - Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. 321-328 - Mehdi M. Mechaik:
Electrical Characterization of Signal Routability and Performance. 329-336 - Steffen Rochel, N. S. Nagaraj:
Full-Chip Signal Interconnect Analysis for Electromigration Reliability. 337-340 - Erik A. McShane, Krishna Shenai:
Correct-by-Design CAD Enhancement for EMI Signal Integrity. 341-346 - Alvernon Walker, Parag K. Lala:
A Transition Based BIST Approach for Passive Analog Circuits. 347-354 - Jin Ding, David Moloney, Xiaojun Wang
Aliasing-Free Space and Time Compactions with Limited Overhead. 355-360 - Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee:
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. 361-368 - Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen:
An Automated Shielding Algorithm and Tool For Dynamic Circuits. 369-374 - Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi:
A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance. 375-378 - Jean-Pierre Gukguen, Pierre Bricaud:
Applying the OpenMORE Assessment Program for IP Cores. 379-
Panel Discussion
- Nader Vasseghi, Rita Glover:
Focus on Quality of Design: Does it Help or Hinder Time to Market? 383-
Quality Definitions and Metrics
- Einar J. Aas:
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. 389-394 - Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh:
Quality of EDA CAD Tools: Definitions, Metrics and Directions. 395-406 - Richard Goldman, Karen Bartleson:
Tool Interoperability is Key to Improved Design Quality. 407- - Michael Keating:
Measuring Design Quality by Measuring Design Complexity. 103-
Low Power Design and Test
- Takayasu Sakurai:
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. 417-424 - Xiaodong Zhang, Kaushik Roy:
Peak Power Reduction in Low Power BIST. 425-432 - Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos:
Low Power BIST for Wallace Tree-Based Fast Multipliers. 433-438 - Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro
Probabilistic Bottom-Up RTL Power Estimation. 439-
Panel Discussion
- Carlo Guardiani, Andrzej J. Strojwas:
Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? 447-
Design for Manufacturability
- Sani R. Nassif:
Design for Variability in DSM Technologies. 451-454 - Alessandra Nardi, Andrea Neviani
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis. 455-460 - Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski:
Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs. 461-466 - Gary W. Maier, Shawn Smith:
Electronic Process Limited Yield. 467-474 - Mehdi M. Mechaik:
Effects of Package Stackups on Microprocessor Performance. 475-
VDSM Capacitive and Inductive Issues
- Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong:
Coupling Noise Analysis for VLIS and ULSI Circuits. 485-490 - Tong Xiao, Malgorzata Marek-Sadowska:
Efficient Delay Calculation in Presence of Crosstalk. 491-498 - Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro:
Crosstalk Aware Static Timing Analysis: A Two Step Approach. 499-504 - Peivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram:
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk. 505-512 - Shen Lin, Norman Chang, O. Sam Nakagawa:
Quick On-Chip Self- and Mutual-Inductance Screen. 513-
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