default search action
Farid N. Najm
Person information
- affiliation: University of Toronto, Canada
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [c103]Cedric Feghali, Farid N. Najm:
Fast Current Constraints Generation for Chip Safety. ISQED 2024: 1-8 - 2023
- [c102]Armen Kteyan
, Valeriy Sukharev
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. ISPD 2023: 124-132 - [c101]Bijan Shahriari, Farid N. Najm:
Fast Electromigration Simulation for Chip Power Grids. ISQED 2023: 1-8 - 2022
- [j48]Valeriy Sukharev
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4837-4850 (2022) - 2020
- [c100]Adam Issa, Valeriy Sukharev, Farid N. Najm
Electromigration Checking Using a Stochastic Effective Current Model. ICCAD 2020: 5:1-5:8
2010 – 2019
- 2019
- [j47]Zahi Moudallal
Power Scheduling With Active RC Power Grids. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 444-457 (2019) - [c99]Zahi Moudallal, Valeriy Sukharev, Farid N. Najm:
Power Grid Fixing for Electromigration-induced Voltage Failures. ICCAD 2019: 1-8 - [c98]Farid N. Najm, Valeriy Sukharev:
Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper). IRPS 2019: 1-10 - 2018
- [j46]Sandeep Chatterjee
Power Grid Electromigration Checking Using Physics-Based Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1317-1330 (2018) - 2017
- [j45]Mohammad Fawaz
Fast Vectorless RLC Grid Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 489-502 (2017) - [j44]Zahi Moudallal, Farid N. Najm
Generating Current Constraints to Guarantee RLC Power Grid Safety. ACM Trans. Design Autom. Electr. Syst. 22(4): 66:1-66:39 (2017) - [c97]Zahi Moudallal, Farid N. Najm:
Power scheduling with active power grids. ICCAD 2017: 466-473 - [c96]Mohammad Fawaz, Farid N. Najm:
Power grid verification under transient constraints. ICCAD 2017: 593-600 - [c95]Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm:
Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems. ICCAD 2017: 659-666 - [c94]Mohammad Fawaz, Farid N. Najm:
Parallel Simulation-Based Verification of RC Power Grids. ISVLSI 2017: 445-452 - 2016
- [j43]Zahi Moudallal, Farid N. Najm:
Generating Current Budgets to Guarantee Power Grid Safety. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1914-1927 (2016) - [j42]Mehmet Avci, Farid N. Najm:
Verification of the Power and Ground Grids Under General and Hierarchical Constraints. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 729-742 (2016) - [c93]Mohammad Fawaz, Farid N. Najm:
Fast simulation-based verification of RC power grids. CCECE 2016: 1-6 - [c92]Mohammad Fawaz, Farid N. Najm:
Accurate verification of RC power grids. DATE 2016: 814-817 - [c91]Abdul-Amir Yassine, Farid N. Najm:
A fast layer elimination approach for power grid reduction. ICCAD 2016: 101 - [c90]Sandeep Chatterjee, Valeriy Sukharev
Fast physics-based electromigration checking for on-die power grids. ICCAD 2016: 110 - [c89]Zahi Moudallal, Farid N. Najm:
Generating voltage drop aware current budgets for RC power grids. ISCAS 2016: 2583-2586 - 2015
- [j41]Sandeep Chatterjee
Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1509-1522 (2015) - [c88]Zahi Moudallal, Farid N. Najm:
Generating circuit current constraints to guarantee power grid safety. ASP-DAC 2015: 358-365 - [c87]Farid N. Najm:
Physical Design Challenges in the Chip Power Distribution Network. ISPD 2015: 101 - 2013
- [c86]Sandeep Chatterjee
Redundancy-aware electromigration checking for mesh power grids. ICCAD 2013: 540-547 - [c85]Mohammad Fawaz, Sandeep Chatterjee
A vectorless framework for power grid electromigration checking. ICCAD 2013: 553-560 - 2012
- [j40]Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm:
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 271-284 (2012) - [j39]Khaled R. Heloue, Sari Onaissi, Farid N. Najm:
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 472-484 (2012) - [c84]Abhishek, Farid N. Najm:
Incremental power grid verification. DAC 2012: 151-156 - [c83]Farid N. Najm:
Overview of vectorless/early power grid verification. ICCAD 2012: 670-677 - 2011
- [j38]Nahi H. Abdul Ghani, Farid N. Najm:
Fast Vectorless Power Grid Verification Under an RLC Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 691-703 (2011) - [c82]Nahi H. Abdul Ghani, Farid N. Najm:
Power grid verification using node and branch dominance. DAC 2011: 682-687 - [c81]Pamela Al Haddad, Farid N. Najm:
Power grid correction using sensitivity analysis under an RC model. DAC 2011: 688-693 - [c80]Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm:
A fast approach for static timing analysis covering all PVT corners. DAC 2011: 777-782 - [c79]Ankit Goyal, Farid N. Najm:
Efficient RC power grid verification using node elimination. DATE 2011: 257-260 - 2010
- [j37]Imad A. Ferzli, Eli Chiprout, Farid N. Najm:
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 92-102 (2010) - [c78]Sean Safarpour, Andreas G. Veneris, Farid N. Najm:
Managing verification error traces with bounded model debugging. ASP-DAC 2010: 601-606 - [c77]Meric Aydonat, Farid N. Najm:
Power grid correction using sensitivity analysis. ICCAD 2010: 808-815 - [c76]Mehmet Avci, Farid N. Najm:
Early P/G grid voltage integrity verification. ICCAD 2010: 816-823
2000 – 2009
- 2009
- [j36]Khaled R. Heloue, Navid Azizi, Farid N. Najm:
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 874-887 (2009) - [j35]Jason Helge Anderson, Farid N. Najm:
Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1048-1060 (2009) - [c75]Nahi H. Abdul Ghani, Farid N. Najm:
Fast vectorless power grid verification using an approximate inverse technique. DAC 2009: 184-189 - [c74]Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
Clock skew optimization via wiresizing for timing sign-off covering all process corners. DAC 2009: 196-201 - [c73]Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm:
Quantifying robustness metrics in parameterized static timing analysis. ICCAD 2009: 209-216 - [c72]Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
PSTA-based branch and bound approach to the silicon speedpath isolation problem. ICCAD 2009: 217-224 - 2008
- [j34]Sari Onaissi, Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1291-1304 (2008) - [j33]Khaled R. Heloue, Farid N. Najm:
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1826-1839 (2008) - [c71]Khaled R. Heloue, Farid N. Najm:
Parameterized timing analysis with general delay models and arbitrary variation sources. DAC 2008: 403-408 - [c70]Khaled R. Heloue, Sari Onaissi, Farid N. Najm:
Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD 2008: 173-180 - 2007
- [j32]Farid N. Najm, Noel Menezes, Imad A. Ferzli:
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 574-591 (2007) - [j31]Navid Azizi, Muhammad M. Khellah
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 746-757 (2007) - [c69]Khaled R. Heloue, Navid Azizi, Farid N. Najm:
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC 2007: 93-98 - [c68]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 - [c67]Imad A. Ferzli, Farid N. Najm, Lars Kruse:
A geometric approach for early power grid verification using current constraints. ICCAD 2007: 40-47 - [c66]Imad A. Ferzli, Farid N. Najm, Lars Kruse:
Early power grid verification under circuit current uncertainties. ISLPED 2007: 116-121 - 2006
- [j30]Imad A. Ferzli, Farid N. Najm:
Analysis and verification of power grids considering process-induced leakage-current variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 126-143 (2006) - [j29]Jason Helge Anderson, Farid N. Najm:
Active leakage power optimization for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 423-437 (2006) - [j28]Srinivas Bodapati, Farid N. Najm:
High-level current macro model for logic blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 837-855 (2006) - [j27]Bin Wu, Jianwen Zhu, Farid N. Najm:
Dynamic-range estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1618-1636 (2006) - [j26]Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm:
Voltage-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2156-2169 (2006) - [c65]Kostas Pagiamtzis
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. CICC 2006: 301-304 - [c64]Georges Nabaa, Navid Azizi, Farid N. Najm:
An adaptive FPGA architecture with process variation compensation and reduced leakage. DAC 2006: 624-629 - [c63]Navid Azizi, Farid N. Najm:
A family of cells to reduce the soft-error-rate in ternary-CAM. DAC 2006: 779-784 - [c62]Nahi H. Abdul Ghani, Farid N. Najm:
Handling inductance in early power grid verification. ICCAD 2006: 127-134 - [c61]Sari Onaissi, Farid N. Najm:
A linear-time approach for static timing analysis covering all process corners. ICCAD 2006: 217-224 - 2005
- [j25]Kavel M. Büyüksahin, Farid N. Najm:
Early power estimation for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1076-1088 (2005) - [j24]Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi:
A Case for Asymmetric-Cell Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 877-881 (2005) - [c60]David T. Blaauw, Anirudh Devgan, Farid N. Najm:
Leakage power: trends, analysis and avoidance. ASP-DAC 2005 - [c59]Navid Azizi, Farid N. Najm:
Look-up table leakage reduction for FPGAs. CICC 2005: 187-190 - [c58]Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling. DAC 2005: 529-534 - [c57]Farid N. Najm:
On the need for statistical timing analysis. DAC 2005: 764-765 - [c56]Bin Wu, Jianwen Zhu, Farid N. Najm:
A non-parametric approach for dynamic range estimation of nonlinear systems. DAC 2005: 841-844 - [c55]Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm:
Incremental partitioning-based vectorless power grid verification. ICCAD 2005: 358-364 - [c54]Khaled R. Heloue, Farid N. Najm:
Statistical timing analysis with two-sided constraints. ICCAD 2005: 829-836 - [c53]Maha Nizam, Farid N. Najm, Anirudh Devgan:
Power grid voltage integrity verification. ISLPED 2005: 239-244 - 2004
- [j23]Jason Helge Anderson, Farid N. Najm:
Power estimation techniques for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1015-1027 (2004) - [c52]Jason Helge Anderson, Farid N. Najm:
Interconnect capacitance estimation for FPGAs. ASP-DAC 2004: 713-718 - [c51]Jason Helge Anderson, Farid N. Najm:
A novel low-power FPGA routing switch. CICC 2004: 719-722 - [c50]Farid N. Najm, Noel Menezes:
Statistical timing analysis based on a timing yield model. DAC 2004: 460-465 - [c49]Bin Wu, Jianwen Zhu, Farid N. Najm:
An analytical approach for dynamic range estimation. DAC 2004: 472-477 - [c48]Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm:
Worst-case circuit delay taking into account power supply variations. DAC 2004: 652-657 - [c47]Jason Helge Anderson, Farid N. Najm, Tim Tuan:
Active leakage power optimization for FPGAs. FPGA 2004: 33-41 - [c46]Jason Helge Anderson, Farid N. Najm:
Low-power programmable routing circuitry for FPGAs. ICCAD 2004: 602-609 - [c45]Bin Wu, Jianwen Zhu, Farid N. Najm:
Dynamic range estimation for nonlinear systems. ICCAD 2004: 660-667 - [c44]Navid Azizi, Farid N. Najm:
An Asymmetric SRAM Cell to Lower Gate Leakage. ISQED 2004: 534-539 - 2003
- [j22]Subodh Gupta, Farid N. Najm:
Energy and peak-current per-cycle estimation at RTL. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 525-537 (2003) - [j21]Navid Azizi, Farid N. Najm, Andreas Moshovos:
Low-leakage asymmetric-cell SRAM. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 701-715 (2003) - [c43]Dionysios Kouroussis, Farid N. Najm:
A static pattern-independent technique for power grid voltage integrity verification. DAC 2003: 99-104 - [c42]Imad A. Ferzli, Farid N. Najm:
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. DAC 2003: 856-859 - [c41]Rubil Ahmadi, Farid N. Najm:
Timing Analysis in Presence of Power Supply and Ground Voltage Variations. ICCAD 2003: 176-183 - [c40]Imad A. Ferzli, Farid N. Najm:
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. ICCAD 2003: 770-777 - [c39]Kavel M. Büyüksahin, Priyadarsan Patra
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. ISLPED 2003: 294-297 - [c38]Rafik S. Guindi, Farid N. Najm:
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. ISQED 2003: 61-65 - [c37]Jason Helge Anderson, Farid N. Najm:
Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP 2003: 15-21 - 2002
- [j20]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
A multigrid-like technique for power grid analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1148-1160 (2002) - [j19]Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
Estimation of state line statistics in sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(3): 455-473 (2002) - [j18]Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
A technique for Improving dual-output domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 508-511 (2002) - [c36]Srinivas Bodapati, Farid N. Najm:
High-level current macro-model for power-grid analysis. DAC 2002: 385-390 - [c35]Jason Helge Anderson, Farid N. Najm:
Power-aware technology mapping for LUT-based FPGAs. FPT 2002: 211-218 - [c34]Navid Azizi, Andreas Moshovos, Farid N. Najm:
Low-leakage asymmetric-cell SRAM. ISLPED 2002: 48-51 - [c33]Kavel M. Büyüksahin, Farid N. Najm:
High-level area estimation. ISLPED 2002: 271-274 - 2001
- [j17]Joseph N. Kozhaya, Farid N. Najm:
Power estimation for large sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 400-407 (2001) - [j16]Srinivas Bodapati, Farid N. Najm:
Prelayout estimation of individual wire lengths. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 943-958 (2001) - [c32]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
Multigrid-Like Technique for Power Grid Analysis. ICCAD 2001: 480-487 - [c31]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
I/O buffer placement methodology for ASICs. ICECS 2001: 245-248 - [c30]Mehrdad Shahriari, Farid N. Najm:
A gate-level timing model for SOI circuits. ICECS 2001: 795-798 - [c29]Srinivas Bodapati, Farid N. Najm:
Frequency-domain supply current macro-model. ISLPED 2001: 295-298 - 2000
- [j15]Subodh Gupta, Farid N. Najm:
Analytical models for RTL power estimation of combinational andsequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 808-814 (2000) - [j14]Subodh Gupta, Farid N. Najm:
Power modeling for high-level power estimation. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 18-29 (2000) - [c28]Kavel M. Büyüksahin, Farid N. Najm:
High-level power estimation with interconnect effects. ISLPED 2000: 197-202 - [c27]Gilbert Yoh, Farid N. Najm:
A Statistical Model for Electromigration Failures. ISQED 2000: 45-50 - [c26]Srinivas Bodapati, Farid N. Najm:
Pre-layout estimation of individual wire lengths. SLIP 2000: 93-98
1990 – 1999
- 1999
- [j13]Mahadevamurty Nemani, Farid N. Najm:
High-level area and power estimation for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 697-713 (1999) - [c25]Subodh Gupta, Farid N. Najm:
Power macro-models for DSP blocks with application to high-level synthesis. ISLPED 1999: 103-105 - [c24]Subodh Gupta, Farid N. Najm:
Energy-per-cycle estimation at RTL. ISLPED 1999: 121-126 - [c23]Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
An optimization technique for dual-output domino logic. ISLPED 1999: 258-260 - [e1]Farid N. Najm, Jason Cong, David T. Blaauw:
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999. ACM 1999, ISBN 1-58113-133-X [contents] - 1998
- [j12]Farid N. Najm, Michael G. Xakellis:
Statistical Estimation of the , Switching Activity in VLSI Circuits. VLSI Design 7(3): 243-254 (1998) - [j11]Farid N. Najm, Gary Yeap:
Guest Editorial. VLSI Design 7(3) (1998) - [j10]Rajendran Panda, Farid N. Najm:
Post-Mapping Transformations for Low-Power Synthesis. VLSI Design 7(3): 289-301 (1998) - [c22]Mahadevamurty Nemani, Farid N. Najm:
Delay Estimation VLSI Circuits from a High-Level View. DAC 1998: 591-594 - 1997
- [c21]Subodh Gupta, Farid N. Najm:
Power Macromodeling for High Level Power Estimation. DAC 1997: 365-370 - [c20]Rajendran Panda, Farid N. Najm:
Technology-Dependent Transformations for Low-Power Synthesis. DAC 1997: 650-655 - [c19]Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
Monte-Carlo approach for power estimation in sequential circuits. ED&TC 1997: 416-420 - [c18]Mahadevamurty Nemani, Farid N. Najm:
High-level area and power estimation for VLSI circuits. ICCAD 1997: 114-119 - [c17]Joseph N. Kozhaya, Farid N. Najm:
Accurate power estimation for large sequential circuits. ICCAD 1997: 488-493 - 1996
- [j9]Mahadevamurty Nemani, Farid N. Najm:
Towards a high-level power estimation capability [digital ICs]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 588-598 (1996) - [c16]Mahadevamurty Nemani, Farid N. Najm:
High-level power estimation and the area complexity of Boolean functions. ISLPED 1996: 329-334 - 1995
- [j8]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 998-1012 (1995) - [c15]Farid N. Najm:
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits. DAC 1995: 612-617 - [c14]Farid N. Najm, Michael Y. Zhang:
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits. DAC 1995: 623-627 - [c13]Farid N. Najm, Shashank Goel, Ibrahim N. Hajj:
Power Estimation in Sequential Circuits. DAC 1995: 635-640 - [c12]Farid N. Najm:
Power estimation techniques for integrated circuits. ICCAD 1995: 492-499 - [c11]Farid N. Najm:
Towards a high-level power estimation capability. ISLPD 1995: 87-92 - 1994
- [j7]Farid N. Najm:
Low-pass filter for computing the transition density in digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1123-1131 (1994) - [j6]Farid N. Najm:
A survey of power estimation techniques in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 446-455 (1994) - [c10]Michael G. Xakellis, Farid N. Najm:
Statistical Estimation of the Switching Activity in Digital Circuits. DAC 1994: 728-733 - [c9]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. ISCAS 1994: 435-438 - 1993
- [j5]Farid N. Najm:
Transition density: a new measure of activity in digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 310-323 (1993) - [j4]Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick:
A Monte Carlo approach for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 1(1): 63-71 (1993) - [c8]Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj:
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. DAC 1993: 384-388 - 1992
- [c7]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits. DAC 1992: 2-7 - [c6]Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick:
McPOWER: a Monte Carlo approach to power estimation. ICCAD 1992: 90-97 - 1991
- [j3]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1372-1381 (1991) - [c5]Farid N. Najm:
Transition Density, A Stochastic Measure of Activity in Digital Circuits. DAC 1991: 644-649 - 1990
- [j2]Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 439-450 (1990) - [j1]Farid N. Najm, Ibrahim N. Hajj:
The complexity of fault detection in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 995-1001 (1990)
1980 – 1989
- 1989
- [b1]Farid N. Najm:
Probabilistic simulation for reliability analysis of VLSI circuits. University of Illinois Urbana-Champaign, USA, 1989 - [c4]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Computation of bus current variance for reliability estimation of VLSI circuits. ICCAD 1989: 202-205 - [c3]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Electromigration median time-to-failure based on a stochastic current waveform. ICCD 1989: 447-450 - 1988
- [c2]Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar:
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. DAC 1988: 294-299 - [c1]Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
CREST-a current estimator for CMOS circuits. ICCAD 1988: 204-207
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 22:06 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: