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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 15
Volume 15, Number 1, January 1996
- Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac:
Unified complete MOSFET model for analysis of digital and analog circuits. 1-7 - Andrew B. Kahng, Chung-Wen Albert Tsao:
Planar-DME: a single-layer zero-skew clock tree router. 8-19 - Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy:
A novel framework for logic verification in a synthesis environment. 20-32 - Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska:
Graph based analysis of 2-D FPGA routing. 33-44 - Ivan P. Radivojevic, Forrest Brewer
:
A new symbolic technique for control-dependent scheduling. 45-57 - Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson:
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. 58-67 - Resve A. Saleh, Brian A. A. Antao, Jaidip Singh:
Multilevel and mixed-domain simulation of analog circuits and systems. 68-82 - Chingwei Yeh, Chi-Shong Wang:
On the integration of partitioning and global routing for rectilinear placement problems. 83-91 - Nikos Glezos, Ioannis Raptis
A fast electron beam lithography simulator based on the Boltzmann transport equation. 92-102 - Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar
Finding obstacle-avoiding shortest paths using implicit connection graphs. 103-110 - Glenn Jennings, Esther Jennings:
A discrete syntax for level-sensitive latched circuits having n clocks and m phases. 111-126 - Jochen Bern, Christoph Meinel, Anna Slobodová:
Some heuristics for generating tree-like FBDD types. 127-130 - Jochen Bern, Christoph Meinel, Anna Slobodová:
Global rebuilding of OBDD's avoiding memory requirement maxima. 131-134
Volume 15, Number 2, February 1996
- Marco Saraniti, Achim Rein, Günther Zandler, Peter Vogl, Paolo Lugli:
An efficient multigrid Poisson solver for device simulations. 141-150 - Miodrag Potkonjak, Mani B. Srivastava, Anantha P. Chandrakasan:
Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. 151-165 - Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani:
Scheduling and control generation with environmental constraints based on automata representations. 166-183 - Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi:
Domain characterization of transmission line models and analyses. 184-193 - Chih-Chuan Lin, Mark E. Law:
2-D mesh adaption and flux discretizations for dopant diffusion modeling. 194-207 - Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng:
A global router with a theoretical bound on the optimal solution. 208-216 - Hsiao-Feng Steven Chen, D. T. Lee:
A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts. 217-227 - Sandeep Bhatia, Niraj K. Jha:
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. 228-243 - Yves Blaquière, Michel R. Dagenais, Yvon Savaria:
Timing analysis speed-up using a hierarchical and a multimode approach. 244-255 - Y. G. Chen, James B. Kuo:
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. 256-258 - Hortensia Mecha
A method for area estimation of data-path in high level synthesis. 258-265
Volume 15, Number 3, March 1996
- Emil S. Ochotta, Rob A. Rutenbar
Synthesis of high-performance analog circuits in ASTRX/OBLX. 273-294 - Ajoy Opal:
Sampled data simulation of linear and nonlinear circuits. 295-307 - Chow Sit Tsang-Ping, Christopher M. Snowden, David M. Barry:
A parallel implementation of an electrothermal simulation for GaAs MESFET devices. 308-316 - Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong
Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. 317-324 - Kevin Cattell, Jon C. Muzio:
Synthesis of one-dimensional linear hybrid cellular automata. 325-335 - Jin-Tai Yan
Minimizing the number of switchboxes for region definition and ordering assignment. 336-347 - Guy Even, Ilan Y. Spillinger, Leon Stok:
Retiming revisited and reversed. 348-357 - Cheng-Hsi Chen, Ioannis G. Tollis:
An Omega(k2) lower bound for area optimization of spiral floorplans. 358-360 - Razak Hossain, Menghui Zheng, Alexander Albicki:
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering. 361-368 - Ogan Ocah, Mehmet Ali Tan, Abdullah Atalar:
A new method for nonlinear circuit simulation in time domain: NOWE. 368-374
Volume 15, Number 4, April 1996
- Shin-ichi Minato:
Fast factorization method for implicit cube set representation. 377-384 - Ning Song, Marek A. Perkowski:
Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions. 385-395 - Jason Cong, Wilburt Labio, Narayanan Shivakumar:
Multiway VLSI circuit partitioning based on dual net representation. 396-409 - Uwe Gläser, Heinrich Theodor Vierhaus:
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. 410-423 - Kyoung-Son Jhang
COP: a Crosstalk OPtimizer for gridded channel routing. 424-429 - Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng:
Performance driven bus buffer insertion. 429-437 - Chiu-sing Choy, Tsz-Shing Cheung, Kam-Keung Wong:
Incremental layout placement modification algorithms. 437-445 - Srinivas Devadas, Kurt Keutzer:
Addendum to "Synthesis of robust delay-fault testable circuits: Theory". 445-446 - Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman:
MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model. 446-451
Volume 15, Number 5, May 1996
- Ping-Chung Li, Ibrahim N. Hajj:
Computer-aided redesign of VLSI circuits for hot-carrier reliability. 453-464 - Tong Gao, C. L. Liu:
Minimum crosstalk channel routing. 465-474 - William R. Bandy, Raymond S. Winton:
A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way. 475-483 - Slobodan Mijalkovic:
Exponentially fitted discretization schemes for diffusion process simulation on coarse grids. 484-492 - Alper Demir
Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. 493-505 - Timo Koskinen, Peter Y. K. Cheung:
Hierarchical tolerance analysis using statistical behavioral models. 506-516 - Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman:
An analysis of fault partitioned parallel test generation. 517-534 - Jin-Fuw Lee, Donald T. Tang, Chak-Kuen Wong:
A timing analysis algorithm for circuits with level-sensitive latches. 535-543 - Florentin Dartu, Noel Menezes, Lawrence T. Pileggi:
Performance computation for precharacterized CMOS gates with RC loads. 544-553 - Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-based multiway FPGA partitioning. 554-560 - Chunghee Kim, Hyunchul Shin:
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. 560-568
Volume 15, Number 6, June 1996
- Paul E. Landman, Jan M. Rabaey:
Activity-sensitive architectural power analysis. 571-587 - Mahadevamurty Nemani, Farid N. Najm:
Towards a high-level power estimation capability [digital ICs]. 588-598 - Diana Marculescu
Information theoretic measures for power analysis [logic design]. 599-610 - Anthony M. Hill, Sung-Mo Kang:
Determining accuracy bounds for simulation-based switching activity estimation. 611-618 - Sven Wuytack, Francky Catthoor, Hugo De Man:
Transforming set data types to power optimal data structures. 619-629 - Luca Benini, Giovanni De Micheli:
Automatic synthesis of low-power gated-clock finite-state machines. 630-643 - Christopher K. Lennard, A. Richard Newton:
On estimation accuracy for guiding low-power resynthesis. 644-664 - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for low power CMOS circuits. 665-671 - Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits. 672-680 - Chor Ping Low, Hon Wai Leong:
Minimum fault coverage in memory arrays: a fast algorithm and probabilistic analysis. 681-690 - Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design. 691-701
Volume 15, Number 7, July 1996
- Antonio Jesús Torralba Silgado
FASY: a fuzzy-logic based tool for analog synthesis. 705-715 - Andrew Lumsdaine
Accelerated waveform methods for parallel transient simulation of semiconductor devices. 716-726 - Chunduri Rama Mohan, Partha Pratim Chakrabarti:
EARTH: combined state assignment of PLA-based FSM's targeting area and testability. 727-731 - Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton:
Permissible functions for multioutput components in combinational logic optimization. 732-744 - Mohammed Hasanuzzaman, Carlos H. Mastrangelo:
Process compilation of thin film microdevices. 745-764 - Benno H. Krabbenborg, A. Bosma, Henk C. de Graaff, Ton J. Mouthaan:
Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures. 765-774 - Jeffrey G. Mueller, Brian A. A. Antao, Resve A. Saleh:
A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. 775-790 - William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Valid clock frequencies and their computation in wavepipelined circuits. 791-807 - Michele Favalli
Modeling and simulation of broken connections in CMOS IC's. 808-814 - Dan Li, Wen-Ben Jone:
Pseudorandom test-length analysis using differential solutions. 815-825 - Chi-Yu Mao, Yu Hen Hu:
Analysis of convergence properties of a stochastic evolution algorithm. 826-831 - Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for synchronous sequential circuits. 831-843
Volume 15, Number 8, August 1996
- Kwang-Ting Cheng
Classification and identification of nonrobust untestable path delay faults. 845-853 - Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
Analysis and synthesis of concurrent digital circuits using control-flow expressions. 854-876 - Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey:
Performance optimization using template mapping for datapath-intensive high-level synthesis. 877-888 - Sasan Iman, Massoud Pedram:
An approach for multilevel logic optimization targeting low power. 889-901 - Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi:
Solving the net matching problem in high-performance chip design. 902-911 - Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
A wire length estimation technique utilizing neighborhood density equations. 912-922 - Enrico Malavasi, Edoardo Charbon, Eric Felt, Alberto L. Sangiovanni-Vincentelli
Automation of IC layout with analog constraints. 923-942 - Maurizio Rebaudengo
GALLO: a genetic algorithm for floorplan area optimization. 943-951 - Youssef Saab:
An improved linear placement algorithm using node compaction. 952-958 - Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi:
Automatic layout recycling based on layout description and linear programming. 959-967 - Joe Rodriguez-Tellez, B. P. Stothard, C. Galvan:
Comparison of temperature models for the drain current of MESFET's. 968-976 - Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram:
OBDD-based function decomposition: algorithms and implementation. 977-990 - Fulvio Corno
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. 991-1000 - Sachin S. Sapatnekar
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. 1001-1011 - Nobuo Funabiki, Seishi Nishikawa:
A neural network model for multilayer topological via minimization in a switchbox. 1012-1020 - Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
A weighted random pattern test generation system. 1020-1025 - Niccolò F. Rinaldi
Fast and simple method for calculating the minority-carrier current in arbitrarily doped semiconductors. 1025-1026
Volume 15, Number 9, September 1996
- Narayan R. Aluru
Simulation of the hydrodynamic device model on distributed memory parallel computers. 1029-1047 - Hyung Ki Lee, Dong Sam Ha:
HOPE: an efficient parallel fault simulator for synchronous sequential circuits. 1048-1058 - Jaewon Kim, Sung-Mo Kang:
A new triple-layer OTC channel router. 1059-1070 - Chennian Di, Jochen A. G. Jess:
An efficient CMOS bridging fault simulator: with SPICE accuracy. 1071-1080 - Manoj Franklin, Kewal K. Saluja:
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. 1081-1087 - Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Fast true delay estimation during high level synthesis. 1088-1105 - Qing Zhu, Wayne Wei-Ming Dai:
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. 1106-1118 - Guy Bois, Eduard Cerny:
Efficient generation of diagonal constraints for 2-D mask compaction. 1119-1126 - Mohankumar Guruswamy, Martin D. F. Wong
Echelon: a multilayer detailed area router. 1126-1136 - Per Larsson-Edefors:
Technology mapping onto very-high-speed standard CMOS hardware. 1137-1144 - Jaushin Lee, Janak H. Patel:
Hierarchical test generation under architectural level functional constraints. 1144-1151 - Mario Alberto López, Ravi Janardan, Sartaj K. Sahni:
Efficient net extraction for restricted orientation designs [VLSI layout]. 1151-1159 - Piyush K. Sancheti, Sachin S. Sapatnekar
Optimal design of macrocells for low power and high speed. 1160-1166 - Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Combinational test generation using satisfiability. 1167-1176 - Massoud Pedram, Sasan Iman:
Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power". 1176
Volume 15, Number 10, October 1996
- Khalid Rahmat, Jacob K. White, Dimitri A. Antoniadis:
Simulation of semiconductor devices using a Galerkin/spherical harmonic expansion approach to solving the coupled Poisson-Boltzmann system. 1181-1196 - Margarida F. Jacome, Stephen W. Director:
A formal basis for design process planning and management. 1197-1210 - Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Incorporating performance and testability constraints during binding in high-level synthesis. 1212-1225 - Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. 1226-1236 - Sachin S. Sapatnekar
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. 1237-1248 - Kuo-Hua Wang, TingTing Hwang, Cheng Chen:
Exploiting communication complexity for Boolean matching. 1249-1256 - Tan-Li Chou, Kaushik Roy:
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. 1257-1265 - Steven E. Laux:
On particle-mesh coupling in Monte Carlo semiconductor device simulation. 1266-1277 - Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. 1278-1285 - José T. de Sousa
Defect level evaluation in an IC design environment. 1286-1293 - Dorit S. Hochbaum:
An optimal test compression procedure for combinational circuits. 1294-1299 - Kazuhiro Tsuchiya, Yoshiyasu Takefuji
A neural network approach to PLA folding problems. 1299-1305
Volume 15, Number 11, November 1996
- Massimo Conti
Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation. 1309-1323 - Aurelio Pellegrini, Luigi Colalongo, Marina Valdinoci, Massimo Rudan:
AC analysis of amorphous silicon devices. 1324-1331 - Alexei D. Sadovnikov, David J. Roulston, D. Celi:
Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods. 1332-1339 - Babette van Antwerpen-de Fluiter, Emile H. L. Aarts, Jan H. M. Korst, Wim F. J. Verhaegh, Albert van der Werf:
The complexity of generalized retiming problems. 1340-1353 - David J. Kolson, Alexandru Nicolau, Nikil D. Dutt
Elimination of redundant memory traffic in high-level synthesis. 1354-1364 - Srinivasa R. Danda, Xiaolin Liu, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis:
Optimal algorithms for planar over-the-cell routing problems. 1365-1378 - Anirudh Devgan:
Transient simulation of integrated circuits in the charge-voltage plane. 1379-1390 - Antonio Jesús Torralba Silgado
Circuit performance modeling by means of fuzzy logic. 1391-1398 - Krishnendu Chakrabarty
Test response compaction using multiplexed parity trees. 1399-1408 - Thomas E. Marchok, Aiman H. El-Maleh
A complexity analysis of sequential ATPG. 1409-1423 - Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. 1424-1434 - Martin Sauerhoff, Ingo Wegener:
On the complexity of minimizing the OBDD size for incompletely specified functions. 1435-1437
Volume 15, Number 12, December 1996
- Zeyi Wang, Yanhong Yuan, Qiming Wu:
A parallel multipole accelerated 3-D capacitance simulator based on an improved model. 1441-1450 - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. 1451-1464 - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi:
Algorithms for approximate FSM traversal based on state space decomposition. 1465-1478 - Gary D. Hachtel, Enrico Macii, Abelardo Pardo
Markovian analysis of large finite state machines. 1479-1493 - Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
Perturb and simplify: multilevel Boolean network optimizer. 1494-1504 - Michael J. Alexander, Gabriel Robins:
New performance-driven FPGA routing algorithms. 1505-1517 - Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
VLSI module placement based on rectangle-packing by the sequence-pair. 1518-1524 - Weiping Shi:
A fast algorithm for area minimization of slicing floorplans. 1525-1532 - Hannah Honghua Yang, Martin D. F. Wong
Balanced partitioning. 1533-1540 - Martin Bächtold, Jan G. Korvink
Enhanced multipole acceleration technique for the solution of large Poisson computations. 1541-1546 - Yun Sik Lee, Peter M. Maurer:
Bit-parallel multidelay simulation. 1547-1554 - Haluk Konuk, F. Joel Ferguson, Tracy Larrabee:
Charge-based fault simulation for CMOS network breaks. 1555-1567 - Chih-Ang Chen, Sandeep K. Gupta:
Design of efficient BIST test pattern generators for delay testing. 1568-1575 - Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
Pin assignment with global routing for VLSI building block layout. 1575-1583 - Tsung-Yi Wu, Youn-Long Lin:
Register minimization beyond sharing among variables. 1583-1587 - Shujian Zhang, D. Michael Miller, Jon C. Muzio:
Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". 1588-1590
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