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ACM Transactions on Reconfigurable Technology and Systems, Volume 11
Volume 11, Number 1, March 2018
- Jason D. Bakos:
Introduction to the Special Section on FCCM'16. - Henry Wong, Vaughn Betz, Jonathan Rose:
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. 1:1-1:22 - James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. 2:1-2:22 - Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). 3:1-3:23
- Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas
, Ganghee Lee, Ediz Cetin
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. 4:1-4:23 - Muhammed Al Kadi
General-Purpose Computing with Soft GPUs on FPGAs. 5:1-5:22 - Kosuke Tatsumura
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. 6:1-6:22 - Rob Stewart
RIPL: A Parallel Image Processing Language for FPGAs. 7:1-7:24 - Farheen Fatima Khan, Andy Gean Ye:
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures. 8:1-8:23
Volume 11, Number 2, November 2018
- Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan, Achintha Ihalage:
Framework for Rapid Performance Estimation of Embedded Soft Core Processors. 9:1-9:21 - Enrico Rossi
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs. 10:1-10:24 - Oleg Petelin
Wotan: Evaluating FPGA Architecture Routability without Benchmarks. 11:1-11:23 - N. Nalla Anandakumar
Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve. 12:1-12:19 - Marc-André Daigneault, Jean-Pierre David:
Automated Synthesis of Streaming Transfer Level Hardware Designs. 13:1-13:22
Volume 11, Number 3, December 2018
- Deming Chen, Andrew Putnam, Steven J. E. Wilton:
Introduction to the Special Section on Deep Learning in FPGAs. 14:1-14:3 - Adrien Prost-Boucle
High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression. 15:1-15:24 - Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. 16:1-16:23 - Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. 17:1-17:24 - Paolo Meloni
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. 18:1-18:24 - Shuanglong Liu
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. 19:1-19:22 - Andrew Boutros
You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. 20:1-20:23 - Bita Darvish Rouhani
ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs. 21:1-21:21 - Jincheng Yu
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA. 22:1-22:23
Volume 11, Number 4, January 2019
- Gai Liu
PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization. 23:1-23:23 - Haomiao Wang
FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL. 24:1-24:25 - Alexander Kroh
Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform. 25:1-25:22 - Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays. 26:1-26:23
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