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Journal of Electronic Testing, Volume 20
Volume 20, Number 1, February 2004
- Vishwani D. Agrawal:
Editorial. 5-6 - A. Ivanov:
Test Technology Technical Council Newsletter. 7-8 - Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski
:
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations. 11-23 - Viera Stopjaková
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. 25-37 - Chun-Lung Hsu:
Control and Observation Structure for Analog Circuits with Current Test Data. 39-44 - Chih-Pin Su, Cheng-Wen Wu
A Graph-Based Approach to Power-Constrained SOC Test Scheduling. 45-60 - Valentin Muresan, Xiaojun Wang
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. 61-78 - Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. 79-87 - Kanad Chakraborty:
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. 89-108 - Ondrej Novák, Zdenek Plíva
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. 109-122
Volume 20, Number 2, April 2004
- Vishwani D. Agrawal:
Editorial. 127 - Paolo Prinetto:
Test Technology Technical Council Newsletter. 131-132 - Lampros Dermentzoglou, Y. Tsiatouhas
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. 133-142 - Rosa Rodríguez-Montañés, D. Muñoz
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. 143-153 - Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin:
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. 155-168 - Nicola Nicolici, Bashir M. Al-Hashimi:
Testability Trade-Offs for BIST Data Paths. 169-179 - Ilia Polian, Bernd Becker
Scalable Delay Fault BIST for Use with Low-Cost ATE. 181-197 - Anshuman Chandra, Krishnendu Chakrabarty
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes. 199-212 - Amit M. Sheth, Jacob Savir:
Scan Latch Design for Test Applications. 213-216
Volume 20, Number 3, June 2004
- Vishwani D. Agrawal:
Editorial. 219 - Paolo Prinetto:
Test Technology Technical Council Newsletter. 221-225 - Petru Cascaval
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories. 227-243 - Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor:
Memory Fault Modeling Trends: A Case Study. 245-255 - Serge Bernard
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. 257-267 - Fulvio Corno
Code Generation for Functional Validation of Pipelined Microprocessors. 269-278 - Mehdi Baradaran Tahoori:
Application-Specific Bridging Fault Testing of FPGAs. 279-289 - Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Distributed Diagnosis of Interconnections in SoC and MCM Designs. 291-307 - Sandeep Koranne:
A Note on System-on-Chip Test Scheduling Formulation. 309-313 - Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. 315-323
Volume 20, Number 4, August 2004
- Vishwani D. Agrawal:
Editorial. 327 - Paolo Prinetto:
Test Technology Technical Council Newsletter. 329 - Fabian Vargas, Víctor H. Champac:
Guest Editorial. 331-332 - Jiang Chau Wang
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. 333-344 - Marcelino B. Santos
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. 345-355 - Érika F. Cota, Luigi Carro
Searching for Global Test Costs Optimization in Core-Based Systems. 357-373 - Florence Azaïs, Serge Bernard
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. 375-387 - Eduardo Romero
Oscillation Test Strategy: A Case Study. 389-396 - Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod:
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems. 397-411 - Dan Alexandrescu, Lorena Anghel
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. 413-421 - Alex Gonsales, Marcelo Lubaszewski, Luigi Carro
A New FPGA for DSP Applications Integrating BIST Capabilities. 423-431 - Maurizio Rebaudengo
A New Approach to Software-Implemented Fault Tolerance. 433-437 - Inali Wisniewski Soares, Silvia Regina Vergilio:
Mutation Analysis and Constraint-Based Criteria: Results from an Empirical Evaluation in the Context of Software Testing. 439-445 - Luis Carlos Erpen De Bona
A Flexible Approach for Defining Distributed Dependable Tests in SNMP-Based Network Management Systems. 447-454
Volume 20, Number 5, October 2004
- Vishwani D. Agrawal:
Editorial. 459 - Paolo Prinetto:
Test Technology Technical Council Newsletter. 461-462 - Cecilia Metra, Matteo Sonza Reorda
Guest Editorial. 463 - Steffen Tarnick:
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes. 465-477 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris
An Analog Checker with Input-Relative Tolerance for Duplicate Signals. 479-488 - Seok-Bum Ko
Efficient Realization of Parity Prediction Functions in FPGAs. 489-499 - Martin Omaña, Daniele Rossi
Model for Transient Fault Susceptibility of Combinational Circuits. 501-509 - Matteo Sonza Reorda
A New Approach to the Analysis of Single Event Transients in VLSI Circuits. 511-521 - Sotirios Matakias, Y. Tsiatouhas
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. 523-531 - André K. Nieuwland, Richard P. Kleihorst:
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors. 533-542 - Bartomeu Alorda, Vincent Canals
A Two-Level Power-Grid Model for Transient Current Testing Evaluation. 543-552 - Amir Rajabzadeh
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features. 553-567
Volume 20, Number 6, December 2004
- Vishwani D. Agrawal:
Editorial. 571 - Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. 575-589 - Soumitra Bose:
Modeling Custom Digital Circuits for Test. 591-609 - Michael Gössel, Krishnendu Chakrabarty
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST. 611-622 - Sunil Rafeeque, Vinita Vasudevan
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. 623-638 - Octavian Petre, Hans G. Kerkhoff:
Scan Test Strategy for Asynchronous-Synchronous Interfaces. 639-645 - Yannick Bonhomme, Patrick Girard
Power-Driven Routing-Constrained Scan Chain Design. 647-660 - Seok-Bum Ko
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs. 661-665 - Lei Li, Krishnendu Chakrabarty
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression. 667-670
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