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IEEE Micro, Volume 37
Volume 37, Number 1, January - February 2017
- Lieven Eeckhout:
Looking Forward to Upcoming Themes. 4-5 - Pradip Bose, Alper Buyuktosunoglu:
Architectural Support for Cognitive Processing. 6-7 - James E. Smith:
Research Agenda: Spacetime Computation and the Neocortex. 8-14 - Yuhao Zhu, Vijay Janapa Reddi, Robert Adolf, Saketh Rama, Brandon Reagen, Gu-Yeon Wei, David M. Brooks:
Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads. 15-21 - Reza Yazdani, Albert Segura, José-María Arnau, Antonio González
:
Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator. 22-29 - Masab Ahmad, Christopher J. Michael, Omer Khan:
Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs. 30-40 - Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk:
Graph Analytics Accelerators for Cognitive Systems. 42-51 - Mateja Putic, A. J. Varshneya, Mircea R. Stan
Hierarchical Temporal Memory on the Automata Processor. 52-59 - Babak Falsafi, Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, Resit Sendag:
FPGAs versus GPUs in Data centers. 60-72 - Richard Mateosian:
Resistance Is Futile. 74-76 - Shane Greenstein:
Technology Policy and the Trump Administration. 78-79
Volume 37, Number 2, March - April 2017
- Lieven Eeckhout:
Hot Chips: Industry and Academia Cutting-Edge Microprocessors. 4 - Bryan Chin, Subhasish Mitra:
Hot Chips 28. 5-6 - Denis Foley, John Danskin:
Ultra-Performance Pascal GPU and NVLink Interconnect. 7-17 - Kaiyuan Guo, Song Han, Song Yao, Yu Wang, Yuan Xie, Huazhong Yang:
Software-Hardware Codesign for Efficient Neural Network Acceleration. 18-25 - Nigel Stephens, Stuart Biles
The ARM Scalable Vector Extension. 26-39 - Satish Kumar Sadasivam
IBM Power9 Processor Architecture. 40-51 - Jack Doweck, Wen-Fu Kao, Allen Kuan-yu Lu, Julius Mandelblat, Anirudha Rahatekar, Lihu Rappoport, Efraim Rotem, Ahmad Yasin, Adi Yoaz:
Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake. 52-62 - Brent Bohnenstiehl, Aaron Stillmaker
KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications. 63-69 - Michael McKeown, Yaosheng Fu, Tri Minh Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Mohammad Shahrad
Piton: A Manycore Processor for Multitenant Clouds. 70-80 - Richard H. Stern:
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery: Part 1. 81-89 - Stavros Volos, Djordje Jevdjic, Babak Falsafi, Boris Grot
Fat Caches for Scale-Out Servers. 90-103 - Margaret Martonosi:
2016 Maurice Wilkes Award Given to Timothy Sherwood. 104-105 - Shane Greenstein:
The Value of Free in GDP. 106-107
Volume 37, Number 3, 2017
- Lieven Eeckhout:
Thoughts on the Top Picks Selections. 4-5 - Aamer Jaleel, Moinuddin K. Qureshi:
Top Picks from the 2016 Computer Architecture Conferences. 6-11 - Yu-Hsin Chen, Joel S. Emer, Vivienne Sze:
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. 12-21 - Mahdi Nazm Bojnordi, Engin Ipek:
The Memristive Boltzmann Machines. 22-29 - Yipeng Huang
Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study. 30-38 - Tony Nowatzki, Vinay Gangadhar, Karthikeyan Sankaralingam, Greg Wright:
Domain Specialization Is Generally Unnecessary for Accelerators. 40-50 - Adrian M. Caulfield, Eric S. Chung, Andrew Putnam
Configurable Clouds. 52-61 - Moein Khazraee, Luis Vega Gutierrez, Ikuo Magaki, Michael Bedford Taylor:
Specializing a Planet's Computation: ASIC Clouds. 62-69 - Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis:
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. 70-78 - Jayneel Gandhi
Agile Paging for Efficient Memory Virtualization. 80-86 - Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi:
Transistency Models: Memory Ordering at the Hardware-OS Interface. 88-97 - James Bornholt, Randolph Lopez, Douglas M. Carmean, Luis Ceze, Georg Seelig, Karin Strauss:
Toward a DNA-Based Archival Storage System. 98-104 - Yazhou Zu, Wei Huang, Indrani Paul
Ti-States: Power Management in Active Timing Margin Processors. 106-114 - Alexei Colin, Graham Harvey, Alanson P. Sample, Brandon Lucia:
An Energy-Aware Debugger for Intermittently Powered Systems. 116-125 - Uri C. Weiser:
Insights from the 2016 Eckert-Mauchly Award Recipient. 126-128 - Shane Greenstein:
Two Sides to Scale. 130-131
Volume 37, Number 4, 2017
- Lieven Eeckhout:
Is Moore's Law Slowing Down? What's Next? 4-5 - Jeffrey S. Vetter, Erik P. DeBenedictis, Thomas M. Conte
Architectures for the Post-Moore Era. 6-8 - Nam Sung Kim, Deming Chen, Jinjun Xiong
Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era. 10-18 - Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. 20-28 - Tim Finkbeiner, Glen Hush, Troy Larsen, Perry Lea, John D. Leidel, Troy Manning:
In-Memory Intelligence. 30-38 - Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang:
Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture. 40-50 - Craig LaBoda, Chris Dwyer, Alvin R. Lebeck:
Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic. 52-62 - Scott M. Jackson, JoAnn M. Paul:
Building Maze Solutions with Computational Dreaming. 64-71 - Richard H. Stern:
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery, Part 2: Apple's Claims. 72-81 - Shane Greenstein:
Moore's Law and Economic Architectures. 82-84
Volume 37, Number 5, September / October 2017
- Lieven Eeckhout:
From Cool Chips to Hot Interconnects. 4-5 - Abhishek Bhattacharjee:
Preserving Virtual Memory by Mitigating the Address Translation Wall. 6-10 - Youchang Kim, Dongjoo Shin, Jinsu Lee, Hoi-Jun Yoo:
BRAIN: A Low-Power Deep Search Engine for Autonomous Robots. 11-19 - Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. 20-31 - Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji
NanoBridge-Based FPGA in High-Temperature Environments. 32-42 - Yuta Tokusashi, Hiroki Matsutani:
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. 44-51 - Omer Arap, Lucas R. B. Brasilino, Ezra Kissel, Alexander Shroyer, Martin Swany
Offloading Collective Operations to Programmable Logic. 52-60 - Richard H. Stern:
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery, Part 3: Determining SEP Reasonable Royalty. 61-69 - Shane Greenstein:
Insider Privileges. 70-72
Volume 37, Number 6, November / December 2017
- Lieven Eeckhout:
Moore's Law and Ultra-Low-Power Processors. 4-5 - Srilatha Manne, Bryan Chin, Steven K. Reinhardt:
If You Build It, Will They Come? 6-12 - Reetuparna Das
Blurring the Lines between Memory and Computation. 13-15 - David Brooks, John Sartori:
Ultra-Low-Power Processors. 16-19 - Mark T. Bohr, Ian A. Young:
CMOS Scaling Trends and Beyond. 20-29 - Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Hoi-Jun Yoo:
Low-Power Convolutional Neural Network Processor for a Face-Recognition System. 30-38 - Hasan Genc, Yazhou Zu, Ting-Wu Chin, Matthew Halpern, Vijay Janapa Reddi:
Flying IoT: Toward Low-Power Vision in the Sky. 40-51 - Vui Seng Chua, Julio Zamora-Esquivel, Anindya Sao Paul, Thawee Techathamnukool, Carlos Flores Fajardo, Nilesh Jain, Omesh Tickoo, Ravi R. Iyer:
Visual IoT: Ultra-Low-Power Processing Architectures and Implications. 52-61 - M. Hassan Najafi
An Overview of Time-Based Computing with Stochastic Constructs. 62-71 - Kaiyuan Yang
Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey. 72-89 - David Brooks:
2017 International Symposium on Computer Architecture Influential Paper Award. 90-91 - Shane Greenstein:
The Hush-Hush Norm. 92-95
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