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Claude Helmstetter
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- affiliation: Synopsys: Montbonnot, France
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2010 – 2019
- 2016
- [j3]Matthieu Moy
, Claude Helmstetter
Modeling Power Consumption and Temperature in TLM Models. Leibniz Trans. Embed. Syst. 3(1): 03:1-03:29 (2016) - 2014
- [j2]Claude Helmstetter
TLM.open: a SystemC/TLM Frontend for the CADP Verification Toolbox. Leibniz Trans. Embed. Syst. 1(1): 02:1-02:18 (2014) - 2013
- [c8]Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC. ASP-DAC 2013: 41-46 - [c7]Claude Helmstetter
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications. DATE 2013: 1185-1188 - 2011
- [i1]Frédéric Blanqui, Claude Helmstetter, Vania Joloboff, Jean-François Monin, Xiaomu Shi:
Designing a CPU model: from a pseudo-formal document to fast code. CoRR abs/1109.4351 (2011)
2000 – 2009
- 2009
- [j1]Claude Helmstetter, Florence Maraninchi
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip. Formal Methods Syst. Des. 35(2): 152-189 (2009) - [c6]Hubert Garavel, Claude Helmstetter
Verification of an industrial SystemC/TLM model using LOTOS and CADP. MEMOCODE 2009: 46-55 - 2008
- [c5]Claude Helmstetter
SimSoC: A SystemC TLM integrated ISS for full system simulation. APCCAS 2008: 1759-1762 - [c4]Jiajia Song, HongWei Hao, Claude Helmstetter
Generation of Executable Representation for Processor Simulation with Dynamic Translation. CSSE (4) 2008: 106-109 - [c3]Claude Helmstetter
A Comparison of Two SystemC/TLM Semantics for Formal Verification. MEMOCODE 2008: 59-68 - 2007
- [b1]Claude Helmstetter:
Validation de modèles de systèmes sur puce en présence d'ordonnancements indéterministes et de temps imprécis. (Validating Models of Systems-on-a-Chip in the Presence of Nondeterministic Schedulings and Loose Timings). Grenoble Institute of Technology, France, 2007 - 2006
- [c2]Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, Matthieu Moy:
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip. FMCAD 2006: 171-178 - [c1]Claude Helmstetter
Test Coverage for Loose Timing Annotations. FMICS/PDMC 2006: 100-115
Coauthor Index
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