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Lukas Kull
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2020 – today
- 2020
- [j11]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg
, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020)
2010 – 2019
- 2019
- [c32]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c31]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC 2019: 112-114 - [c30]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - 2018
- [j10]Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits 53(3): 861-872 (2018) - [j9]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [j8]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(11): 3268-3279 (2018) - [j7]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(12): 3508-3516 (2018) - [j6]Hazar Yueksel, Matthias Braendli
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3529-3542 (2018) - [c29]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS 2018: 1-5 - [c28]Christian Menolfi, Matthias Braendli
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. ISSCC 2018: 104-106 - [c27]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC 2018: 266-268 - [c26]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. ISSCC 2018: 358-360 - [c25]Thomas Toifl, Christian Menolfi, Matthias Brändli
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits 2018: 53-54 - [c24]Pier Andrea Francese
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits 2018: 267-268 - [c23]Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. VLSI Circuits 2018: 275-276 - 2017
- [j5]Ilter Özkaya
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [c22]Lukas Kull, Danny Luu:
Measurement of high-speed ADCs. CICC 2017: 1-7 - [c21]Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC 2017: 115-118 - [c20]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC 2017: 183-186 - [c19]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC 2017: 474-475 - [c18]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - [i1]Abu Sebastian, Tomas Tuma, Nikolaos Papandreou, Manuel Le Gallo, Lukas Kull, Thomas P. Parnell, Evangelos Eleftheriou:
Temporal correlation detection using computational phase-change memory. CoRR abs/1706.00511 (2017) - 2016
- [j4]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits 51(3): 636-648 (2016) - [c17]Hazar Yueksel, Matthias Braendli
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC 2016: 309-312 - [c16]Thomas Toifl, Matthias Braendli
Design considerations for 50G+ backplane links. ESSCIRC 2016: 477-482 - [c15]Pier Andrea Francese
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC 2016: 408-409 - 2015
- [c14]Hazar Yueksel, Lukas Kull, Andreas Burg
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC 2015: 148-151 - [c13]Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese
20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. ISSCC 2015: 1-3 - [c12]Pier Andrea Francese
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC 2015: 1-3 - [c11]Lukas Kull:
Challenges in implementing high-speed, low-power ADCs in CMOS. OFC 2015: 1-3 - [c10]Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC 2015: 228- - 2014
- [j3]Pier Andrea Francese
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits 49(11): 2490-2502 (2014) - [c9]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. A-SSCC 2014: 89-92 - [c8]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ESSCIRC 2014: 135-138 - [c7]Pier Andrea Francese
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC 2014: 435-438 - [c6]Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC 2014: 455-458 - [c5]Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. ISSCC 2014: 90-91 - [c4]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC 2014: 378-379 - 2013
- [j2]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits 48(12): 3049-3058 (2013) - [j1]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits 48(12): 3268-3284 (2013) - [c3]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC 2013: 310-311 - [c2]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC 2013: 408-409 - [c1]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC 2013: 468-469
Coauthor Index
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