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CICC 2017: Austin, TX, USA
- 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017. IEEE 2017, ISBN 978-1-5090-5191-5
- Hans Stork:
Autonomy through smart sensors and power electronics. 1 - Xuqiang Zheng, Fangxu Lv, Feng Zhao
, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang:
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. 1-4 - Joshua Liang
Jitter injection for on-chip jitter measurement in PI-based CDRs. 1-4 - Kwanseo Park
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. 1-4 - Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone
A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer. 1-4 - Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone
Low-power CMOS receivers for short reach optical communication. 1-8 - Eric Naviasky, Mohammad Hekmat:
Session 11 - Wireline building blocks. 1 - Abhirup Lahiri, Pradeep Badrathwal, Nitin Jain, Kallol Chatterjee:
A 0.5V supply, 49nW band-gap reference and crystal oscillator in 40nm CMOS. 1-4 - Dongkwun Kim, Wanyeong Jung, Sechang Oh, Kyojin David Choo
A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference. 1-4 - Hani Esmaeelzadeh, Sudhakar Pamarti
A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators. 1-4 - Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 0.7V time-based inductor for fully integrated low bandwidth filter applications. 1-4 - Yang Xu, Jason Muhlestein, Un-Ku Moon:
A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling. 1-4 - Nagendra Krishnapura
Session 12-Analog techniques I. 1 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy:
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. 1-4 - Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park
A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication. 1-4 - Sandip Ray:
System-on-chip security assurance for IoT devices: Cooperations and conflicts. 1-4 - Teng Yang, Jiangyi Li, Minhao Yang, Peter R. Kinget
An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function. 1-4 - Swaroop Ghosh, Xin Li:
Session 13 - Security circuits and systems. 1 - Earl McCune:
Energy efficiency maxima for wireless communications: 5G, IoT, and massive MIMO. 1-8 - Vivek Mangal
An ultra-low-power wake-up receiver with voltage-multiplying self-mixer and interferer-enhanced sensitivity. 1-4 - Yining Zhang, Ranran Zhou
A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies. 1-4 - Woogeun Rhee
Session 15 - Energy-efficient wireless for 5G and IoT. 1 - Sebastian Strache, Leo Rolff, Stefan Dietrich, Michael Hanhart, Tobias Zekorn, Ralf Wunderlich, Stefan Heinen:
A digital pulse width modulation closed loop control LDMOS gate driver for LED drivers implemented in a 0.18 μm HV CMOS technology. 1-4 - Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. 1-4 - Tianting Zhao, Yue Zhuo, Baoxing Chen
An isolated DC-DC converter with fully integrated magnetic core transformer. 1-4 - Francesco Santoro, Rüdiger Kuhn, Neil Gibson, Nicola Rasera, Thomas Tost, Doris Schmitt-Landsiedel, Ralf Brederlow
A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up. 1-4 - Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai:
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. 1-4 - Luca Intaschi, Paolo Bruschi, Giuseppe Iannaccone
A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvesting. 1-4 - Zhe Hua, Hoi Lee:
A 1.2A auto-configurable dual-output switched-capacitor DC-DC regulator with continuous gate-drive modulation achieving <0.01mV/mA cross regulation. 1-4 - Saurabh Chaubey, Ramesh Harjani:
Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges. 1-4 - Vivienne Sze, Yu-Hsin Chen, Joel S. Einer, Amr Suleiman, Zhengdong Zhang:
Hardware for machine learning: Challenges and opportunities. 1-8 - Muqing Liu, Luke R. Everson, Chris H. Kim:
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities. 1-4 - Xinjie Guo, Farnood Merrikh-Bayat, Mirko Prezioso, Y. Chen, B. Nguyen, N. Do, Dmitri B. Strukov
Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells. 1-4 - Laura Fick, David T. Blaauw, Dennis Sylvester, Skylar Skrzyniarz, Malav Parikh, David Fick:
Analog in-memory subthreshold deep neural network accelerator. 1-4 - Advait Madhavan, Timothy Sherwood
A 4-mm2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions. 1-4 - Brian R. La Cour
Using quantum emulation for advanced computation. 1-8 - Axel Thomsen, Paul Billig:
Session 17 non-traditional computing. 1 - Dongyi Liao, Fa Foster Dai, Bram Nauta
Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking. 1-4 - Ruixin Wang, Fa Foster Dai:
A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression. 1-4 - Hechen Wang
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization. 1-4 - Jabeom Koo, Keping Wang, Richard C. Ruby, Brian P. Otis:
A 350uW 2GHz FBAR transformer coupled Colpitts oscillator with close-in phase noise reduction. 1-4 - Yanjie Wang, Hua Wang
Session 19 - High performance and low power frequency generation. 1 - Aaron Buchwald:
A supposedly clever thing i'll never do again. 1-8 - Aurangozeb
Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver. 1-4 - Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. 1-4 - Jeffrey Lee, Sudhakar Pamarti
A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancement. 1-4 - Sudip Shekhar, Tod Dickson:
Session 2 - Wireline techniques for advanced modulation schemes. 1 - Eric A. M. Klumperink, Hugo J. Westerveld, Bram Nauta
N-path filters and mixer-first receivers: A review. 1-8 - Reda Kasri, Eric A. M. Klumperink, Philippe Cathelin, Eric Toumier, Bram Nauta
A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers. 1-4 - M. H. Koroglu, A. L. Coban, V. M. Pereira, F. Barale, S. X. Wu, W. Yu, R. Sun, K. Pentakota:
A scalable architecture for fully integrated multi-TV tuners. 1-4 - Qiwei Wang, Hajime Shibata, Anthony Chan Carusone
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. 1-4 - Amir Hossein Masnadi Shirazi, Hossein Miri Lavasani
A 980μW 5.2dB-NF current-reused direct-conversion bluetooth-low-energy receiver in 40nm CMOS. 1-4 - Julian Tham, Hossein Miri Lavasani:
Session 20 - High-performance low-power wireless receivers. 1 - Edward K. F. Lee:
A ±5V, ±10V, ±15V, 4-channel class-G biphasic constant-current stimulator. 1-4 - Siddharth Joshi, Chul Kim, Sohmyung Ha
From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing. 1-9 - Yu Chen, Rajit Manohar, Yannis P. Tsividis:
Design of tunable digital delay cells. 1-4 - M. Stockinger, R. Mertens:
RC-triggered ESD clamp with low turn-on voltage. 1-4 - Yi Luo, Shahriar Mirabbasi:
A CMOS pixel design with binary space-time exposure encoding for computational imaging. 1-4 - Farhan Adil, Jiangfeng Wu:
Session 21 - Analog techniques II. 1 - Masaya Miyahara, Akira Matsuzawa:
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. 1-4 - Khiem Nguyen, Michael Determan, Sejun Kim:
A 2.4mW, 111dB SNR continuous-time ΣΔ ADC with a three-level DEM technique. 1-4 - Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. 1-4 - Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow:
Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. 1-4 - Harald Garvik, Carsten Wulff, Trond Ytterdal:
An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation. 1-4 - Yi Zhang, Chia-Hung Chen, Tao He, Kazuki Sobue, Koichi Hamashita, Gabor C. Temes:
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. 1-4 - Neelakantan Narasimman, Dipankar Nag, Kevin Tshun Chuan Chai, Tony T. Kim:
A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation. 1-4 - Nima Maghari, Ivan John O'Connell
Session 22 - Oversampling data converters. 1 - Tolga Dinc, Harish Krishnaswamy:
Millimeter-wave full-duplex wireless: Applications, antenna interfaces and systems. 1-8 - Taiyun Chi, Hechen Wang
A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication. 1-4 - Alit Apriyana, Guangyin Feng
An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS. 1-4 - Oscar Elisio Mattia, Davide Guermandi, Guy Torfs, Piet Wambacq:
An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS. 1-4 - John Long, Fa Foster Dai:
Session 24-Milimeter-wave communication circuits. 1 - Samantak Gangopadhyay, Saad Bin Nasir
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. 1-4 - Younghyun Lim
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. 1-4 - Tarun Mahajan, Ramnarayanan Muthukaruppan, Dheeraj M. Shetty, Sumedha Mangal, Harish Kumar Krishnamurthy:
Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS. 1-4 - Nikolaos Papadopoulos, Florian De Roose, Yi-Cheng Lai, Jan-Laurens P. J. van der Steen, Marc Ameys, Wim Dehaene, Jan Genoe
Flexible selfbiased 66.7nJ/c.s. 6bit 26S/s successive-approximation C-2C ADC with offset cancellation using unipolar Metal-Oxide TFTs. 1-4 - Adelson Chua
Smart-wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor node. 1-4 - Benjamin Krueger, Robert Elvis Makon, Oliver Landolt, Ols Hidri, Thomas Schweiger, Edgar Krune, Dieter Knoll, Stefan Lischke, Joerg Schulze
A monolithically integrated, optically clocked 10 GS/s sampler with a bandwidth of >30 GHz and a jitter of <30 fs in photonic SiGe BiCMOS technology. 1-4 - Christophe Antoine, Marco Tartagni:
Session 27 - Technology directions. 1 - Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon:
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. 1-4 - Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. 1-4 - Shravan S. Nagam, Peter R. Kinget
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation. 1-4 - Eythan Familier, Ian Galton:
Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs. 1-4 - Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. 1-4 - Sudhakar Pamarti
Session 3 - Clocking techniques. 1 - Tianshi Wang:
Modelling multistability and hysteresis in ESD clamps, memristors and other devices. 1-10 - Aikaterini Papadopoulou, Borivoje Nikolic
A yield optimization methodology for mixed-signal circuits. 1-4 - Lukas Kull, Danny Luu:
Measurement of high-speed ADCs. 1-7 - Colin McAndrew, Tetsuya Iizuka:
Session 4 - Modeling and measurement of mixed-signal circuits. 1 - Xiaowei Han, Qian Jia, Hongbin Sun, Longfei Wang, Huaqiang Wu, Yimao Cai, Feng Zhang, Yongyi Xie, Fangxu Dong, Xiaoguang Wang, Xiaofei Xue, Li Pang, Xiaoqing Zhao, Mengnan Wu, Pu Bai, Qi Liu, Hangbing Lv, Bing Yu, Chao Zhao, He Qian, Ru Huang, Ming Liu, Yumei Zhou, Nanning Zheng, Qiwei Ren:
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. 1-4 - Rajiv V. Joshi, Matthew M. Ziegler:
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. 1-4 - Yoshiaki Deguchi
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. 1-4 - Arijit Banerjee
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. 1-4 - Avishek Biswas, Umut Arslan, Fatih Hamzaoglu, Anantha P. Chandrakasan:
An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS. 1-4 - Muhammad M. Khellah
Session 5 - Memory for emerging applications. 1 - Hossein Hashemi
Millimeter-wave power amplifiers & transmitters. 1-8 - Huizhen Jenny Qian, Jian Orion Liang, Nianyong Zhu, Peng Gao, Xun Luo:
A 3-7GHz 4-element digital modulated polar phased-array transmitter with 0.35° phase resolution and 38.2% peak system efficiency. 1-4 - Ali Azam, Zhidong Bai, Wen Yuan
SCPA revolution: Linearization of multiphase SCPAs. 1-8 - Ali Shirvani, K. J. Koh:
Session 6 - RF and millimeter-wave power amplifiers and transmitters. 1 - Yeonam Yoon, Nan Sun:
A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration. 1-4 - Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun:
A pipelined SAR ADC reusing the comparator as residue amplifier. 1-4 - Spencer Leuenberger, Jason Muhlestein, Hyuk Sun, Praveen Kumar Venkatachala, Un-Ku Moon:
A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier. 1-4 - Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar:
A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm using novel residue boosting. 1-4 - Michael Q. Le, James Gorecki, Jamal Riani, Jorge Pernillo, A. Tan, K. Gopalakrishnan, Belal Helal, Pulkit Khandelwal, Chang-Feng Loi, Irene Quek, P. Wong, Aaron Buchwald:
A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS. 1-4 - Jeonggoo Song, Xiyuan Tang, Nan Sun:
A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS. 1-4 - Jason Muhlestein, Spencer Leuenberger, Hyuk Sun, Yang Xu, Un-Ku Moon:
A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization. 1-4 - Ayman Shabra, Dong-Young Chang:
Session 7 - Data converter techniques. 1 - Chul Kim, Sohmyung Ha
Design of miniaturized wireless power receivers for mm-sized implants. 1-8 - Philipp Schönle
A power-efficient multi-channel PPG ASIC with 112dB receiver DR for pulse oximetry and NIRS. 1-4 - Somok Mondal
A dynamically reconfigurable ECG analog front-end with a 2.5 × data-dependent power reduction. 1-4 - Guoqing Fu, Sameer Sonkusale:
CMOS sensor for dual fluorescence intensity and lifetime sensing using multicycle charge modulation. 1-4 - JinSeok Lee
A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring. 1-4 - Mingliang Tan
A front-end ASIC with high-voltage transmit switching and receive digitization for forward-looking intravascular ultrasound. 1-4 - Arthur Kalb, Yogesh Sharma, Juha Virtanen:
Interference-immune diagnostic quality ECG recording for patient monitoring applications. 1-4 - Jong Seok Park, Moez Karim Aziz, Sandra Gonzalez, Doohwan Jung, Taiyun Chi, Sensen Li, Hee Cheol Cho, Hua Wang
A CMOS 22k-pixel single-cell resolution multi-modality real-time cellular sensing array. 1-4 - Pedram Mohseni, Kaushik Sengupta
Session 8 - Biomedical circuits and systems. 1 - Amr Fahim:
mmWave LO distribution insights. 1-72 - John R. Long:
On-chip transformer design and application to RF and mm-wave front-ends. 1-43 - Srevats Laxman:
Equalization algorithms in Millimeter wave communication systems. 1-38 - Nathan Carter:
Achieving higher linearity in precision standard products. 1-45 - Edgar Sánchez-Sinencio:
Analog filter design: Current design techniques and trends. 1-76 - Khiem Nguyen:
Practical dynamic element matching techniques for 3-level unit elements. 1-87 - Yong Lian
Energy efficient system architecture for wireless wearable biomedical sensors. 1-33 - Susanne Paul:
Leveraging the strengths of female engineers in today's business environment. 1-42 - Lawrence T. Clark, Vinay Vashishtha:
Design with sub-10 nm FinFET technologies. 1-87 - Andreia Cathelin:
RF/analog and mixed-signal design techniques in FD-SOI technology. 1-53 - Pavan Kumar Hanumolu:
Time-based ΑΣADCs. 1-44 - Hui Pan
A/D converter fundamentals and trends. 1-102 - Ramesh Harjani:
Integrated DC-DC converter design. 1-92 - Hanh-Phuc Le
ES4-4: Circuit design techniques for fully integrated voltage regulator using switched capacitors. 1-69
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