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Jaehyouk Choi
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2020 – today
- 2024
- [j32]Juyeop Kim
, Yongwoo Jo
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. IEEE J. Solid State Circuits 59(2): 424-434 (2024) - [j31]Seheon Jang
A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. IEEE J. Solid State Circuits 59(12): 3884-3897 (2024) - [c38]Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi:
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. ISSCC 2024: 190-192 - [c37]Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi:
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. ISSCC 2024: 196-198 - 2023
- [j30]Suneui Park
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. IEEE J. Solid State Circuits 58(1): 78-89 (2023) - [j29]Yongwoo Jo
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. IEEE J. Solid State Circuits 58(12): 3338-3350 (2023) - [c36]Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi:
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter. CICC 2023: 1-2 - [c35]Yongwoo Jo
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. ISSCC 2023: 76-77 - [c34]Jooeun Bang
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. ISSCC 2023: 84-85 - [c33]Byeong-Taek Moon
A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. ISSCC 2023: 364-365 - [c32]Yuhwan Shin, Yongwoo Jo
A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. ISSCC 2023: 408-409 - [c31]Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi:
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j28]Younghyun Lim
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. IEEE J. Solid State Circuits 57(2): 480-491 (2022) - [j27]Suneui Park
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. IEEE J. Solid State Circuits 57(9): 2829-2840 (2022) - [j26]Chanwoong Hwang
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. IEEE J. Solid State Circuits 57(9): 2841-2855 (2022) - [j25]Hangi Park
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. IEEE J. Solid State Circuits 57(12): 3527-3537 (2022) - [c30]Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi:
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. ISSCC 2022: 1-3 - [c29]Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi:
A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. ISSCC 2022: 378-380 - 2021
- [j24]Seyeon Yoo
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. IEEE J. Solid State Circuits 56(1): 298-309 (2021) - [c28]Jooeun Bang
A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency. ESSCIRC 2021: 351-354 - [c27]Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi:
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. ISSCC 2021: 330-332 - [c26]Wei Deng, Jaehyouk Choi, Wanghua Wu:
Session 32 Overview: Frequency Synthesizers Rf Subcommittee. ISSCC 2021: 440-441 - [c25]Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi:
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. ISSCC 2021: 442-444 - [c24]Juyeop Kim
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. ISSCC 2021: 448-450 - 2020
- [j23]David T. Blaauw
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 55(12): 3127-3130 (2020) - [c23]Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi:
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. ISSCC 2020: 266-268 - [c22]Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. ISSCC 2020: 270-272 - [c21]Younghyun Lim
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. ISSCC 2020: 280-282
2010 – 2019
- 2019
- [j22]Seojin Choi
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. IEEE J. Solid State Circuits 54(4): 927-936 (2019) - [j21]Heein Yoon
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. IEEE J. Solid State Circuits 54(6): 1564-1574 (2019) - [j20]Taeho Seong
A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC. IEEE J. Solid State Circuits 54(9): 2501-2512 (2019) - [j19]Juyeop Kim
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE J. Solid State Circuits 54(12): 3466-3477 (2019) - [c20]Juyeop Kim
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. ISSCC 2019: 258-260 - [c19]Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator. ISSCC 2019: 490-492 - [c18]Jeonghyun Lee
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer. VLSI Circuits 2019: 130- - 2018
- [j18]Seyeon Yoo
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. IEEE J. Solid State Circuits 53(2): 375-388 (2018) - [j17]Yongsun Lee
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. IEEE J. Solid State Circuits 53(4): 1192-1202 (2018) - [j16]Kyoohyun Lim
A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations. IEEE J. Solid State Circuits 53(7): 1960-1976 (2018) - [j15]Younghyun Lim
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J. Solid State Circuits 53(9): 2675-2685 (2018) - [c17]Younghyun Lim
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. ASP-DAC 2018: 299-300 - [c16]Seyeon Yoo, Seojin Choi
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. ASP-DAC 2018: 303-304 - [c15]Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
A switched-loop-filter PLL with fast phase-error correction technique. ASP-DAC 2018: 307-308 - [c14]Younghyun Lim
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector. ESSCIRC 2018: 210-213 - [c13]Jiayoon Ru, Jaehyouk Choi, Piet Wambacq:
Session 15 overview: RF PLLs: RF subcommittee. ISSCC 2018: 244-245 - [c12]Heein Yoon, Juyeop Kim
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. ISSCC 2018: 366-368 - [c11]Taeho Seong
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. ISSCC 2018: 396-398 - [c10]Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. VLSI Circuits 2018: 185-186 - 2017
- [j14]Younghyun Lim
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3006-3018 (2017) - [c9]Suneui Park, Heein Yoon
An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. A-SSCC 2017: 329-332 - [c8]Younghyun Lim
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. CICC 2017: 1-4 - [c7]Seyeon Yoo, Seojin Choi
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. ISSCC 2017: 324-325 - 2016
- [j13]Mina Kim, Seojin Choi, Taeho Seong
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells. IEEE J. Solid State Circuits 51(2): 401-411 (2016) - [j12]Heein Yoon
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. IEEE J. Solid State Circuits 51(3): 614-625 (2016) - [j11]Seojin Choi, Seyeon Yoo, Younghyun Lim
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector. IEEE J. Solid State Circuits 51(8): 1878-1889 (2016) - [c6]Seojin Choi
10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. ISSCC 2016: 194-195 - [c5]Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop. VLSI Circuits 2016: 1-2 - 2015
- [j10]Donguk Kim, Subin Choi, Jaehyouk Choi
A Reconfigurable Multiphase $LC$-Ring Structure for Programmable Frequency Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 51-55 (2015) - [j9]Yongsun Lee, Mina Kim, Taeho Seong
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 635-644 (2015) - [j8]Taeho Seong
Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 781-790 (2015) - [j7]Yesung Kang, Jaehyouk Choi
A Wide-Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology Node. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 846-850 (2015) - [c4]Mina Kim, Seojin Choi
A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells. VLSIC 2015: 142- - [c3]Eunji Lim, Youngmin Kim, Jaehyouk Choi
Optimization of analog circuits via simulation and a lagrangian-type gradient-based method. WSC 2015: 1206-1217 - 2014
- [j6]Heein Yoon
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 289-293 (2014) - [j5]Taeho Seong
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 701-705 (2014) - 2013
- [j4]Yiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi
A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 1991-2000 (2013) - 2012
- [j3]Jaehyouk Choi
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 969-973 (2012) - [c2]Yiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi
A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation. CICC 2012: 1-4 - 2011
- [j2]Jaehyouk Choi
A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 701-705 (2011) - 2010
- [b1]Jaehyouk Choi:
Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems. Georgia Institute of Technology, Atlanta, GA, USA, 2010 - [j1]Taejoong Song, Jongmin Park, Sang Min Lee, Jaehyouk Choi
A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 188-192 (2010) - [c1]Stephen T. Kim, Jaehyouk Choi
Subthreshold current mode matrix determinant computation for analog signal processing. ISCAS 2010: 1260-1263
Coauthor Index
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