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2020 – today
- 2024
- [j6]Juyeop Kim
, Yongwoo Jo
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. IEEE J. Solid State Circuits 59(2): 424-434 (2024) - [j5]Seheon Jang
A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. IEEE J. Solid State Circuits 59(12): 3884-3897 (2024) - [c8]Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi:
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. ISSCC 2024: 190-192 - 2023
- [j4]Yongwoo Jo
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. IEEE J. Solid State Circuits 58(12): 3338-3350 (2023) - [c7]Yongwoo Jo
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. ISSCC 2023: 76-77 - 2022
- [j3]Chanwoong Hwang
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. IEEE J. Solid State Circuits 57(9): 2841-2855 (2022) - [j2]Hangi Park
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. IEEE J. Solid State Circuits 57(12): 3527-3537 (2022) - [c6]Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi:
A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. ISSCC 2022: 378-380 - 2021
- [c5]Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi:
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. ISSCC 2021: 442-444 - [c4]Juyeop Kim
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. ISSCC 2021: 448-450 - 2020
- [c3]Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi:
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. ISSCC 2020: 266-268 - [c2]Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. ISSCC 2020: 270-272 - [c1]Younghyun Lim
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. ISSCC 2020: 280-282
2010 – 2019
- 2019
- [j1]Juyeop Kim
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE J. Solid State Circuits 54(12): 3466-3477 (2019)
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