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Saptadeep Pal
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2020 – today
- 2024
- [j3]Newsha Ardalani
, Saptadeep Pal
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. ACM Trans. Design Autom. Electr. Syst. 29(2): 30:1-30:20 (2024) - [c11]Shuangliang Chen, Saptadeep Pal, Rakesh Kumar:
Waferscale Network Switches. ISCA 2024: 215-229 - 2023
- [c10]Alexander Graening, Saptadeep Pal, Puneet Gupta
Chiplets: How Small is too Small? DAC 2023: 1-6 - 2022
- [i2]Newsha Ardalani, Saptadeep Pal, Puneet Gupta:
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. CoRR abs/2211.03309 (2022) - 2021
- [b1]Saptadeep Pal:
Scale-Out Packageless Processing. University of California, Los Angeles, USA, 2021 - [c9]Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti
Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC 2021: 1183-1188 - 2020
- [j2]Saptadeep Pal
Design Space Exploration for Chiplet-Assembly-Based Processors. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1062-1073 (2020) - [c8]Saptadeep Pal, Puneet Gupta
Pathfinding for 2.5D interconnect technologies. SLIP 2020: 3
2010 – 2019
- 2019
- [j1]Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training. IEEE Micro 39(5): 91-101 (2019) - [c7]Saptadeep Pal, Daniel Petrisko
Architecting Waferscale Processors - A GPU Case Study. HPCA 2019: 250-263 - [c6]Irina Alam, Saptadeep Pal, Puneet Gupta
Compression with multi-ECC: enhanced error resiliency for magnetic memories. MEMSYS 2019: 85-100 - [i1]Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta:
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training. CoRR abs/1907.13257 (2019) - 2018
- [c5]Saptadeep Pal, Daniel Petrisko
A Case for Packageless Processors. HPCA 2018: 466-479 - 2017
- [c4]Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. DATE 2017: 1438-1443 - [c3]Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta
Advanced Packaging and Heterogeneous Integration to Reboot Computing. ICRC 2017: 1-6 - 2014
- [c2]Saptadeep Pal, K. K. Soundra Pandian
FPGA implementation of stream cipher using Toeplitz Hash function. ICACCI 2014: 1834-1838 - [c1]Saptadeep Pal, Cezary Zukowski, Avishek Nag, David B. Payne, Marco Ruffini:
Cable length minimisation in long-reach-PON planning for sparsely populated areas. ONDM 2014: 234-239
Coauthor Index
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