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ACM Transactions on Design Automation of Electronic Systems, Volume 29
Volume 29, Number 1, January 2024
- Tianming Ni
, Xiaoqing Wen
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware. 1:1-1:3 - Yijun Cui
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA. 2:1-2:20 - Taixin Li
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories. 3:1-3:18 - Zijin Pan
On-chip ESD Protection Design Methodologies by CAD Simulation. 4:1-4:41 - Jingchang Bian
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations. 5:1-5:16 - Yuan Zhang
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing. 6:1-6:19 - Dong Xiang
Test Compression for Launch-on-Capture Transition Fault Testing. 7:1-7:20 - Yongtian Bi
AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems. 8:1-8:19 - Paul Calzada
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM. 9:1-9:25 - Xiaole Cui
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. 10:1-10:21 - Jie Xiao
ICP-RL: Identifying Critical Paths for Fault Diagnosis Using Reinforcement Learning. 11:1-11:20 - Nanlin Guo
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation. 12:1-12:17 - Qingsong Peng
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. 13:1-13:17 - Rihui Sun
Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs. 14:1-14:22
- Enes Saglican
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark. 15:1-15:23 - Martin Rapp
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores. 16:1-16:23 - Monzurul Islam Dewan
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. 17:1-17:28 - Vidya A. Chhabria
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. 18:1-18:25 - Shailja Pandey
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. 19:1-19:35 - Chen Bai
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. 20:1-20:23 - Wanqian Li
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators. 21:1-21:24 - Dan Wu
Flip: Data-centric Edge CGRA Accelerator. 22:1-22:25
- Ying Wu
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits. 23:1-23:37
Volume 29, Number 2, March 2024
- Tung-Che Liang
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips. 24:1-24:24 - Yu Qian
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. 25:1-25:33 - Bo Wang
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow. 26:1-26:32 - Jaspinder Kaur
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. 27:1-27:22 - Seok Young Kim
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference. 28:1-28:22 - Linwei Niu
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing. 29:1-29:35 - Newsha Ardalani
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. 30:1-30:20 - S. Deepanjali
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware. 31:1-31:29 - Yi-Chen Lu
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning. 32:1-32:17 - Libing Deng
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking. 33:1-33:26 - Syam Sankar
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans. 34:1-34:25 - Bo-Yuan Huang
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. 35:1-35:25 - Ke Tang
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins. 36:1-36:18 - Karthik Somayaji Nanjangud Suryanarayana
Pareto Optimization of Analog Circuits Using Reinforcement Learning. 37:1-37:14 - Danping Jiang
RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA. 38:1-38:24 - Jianfeng Wang
A Module-Level Configuration Methodology for Programmable Camouflaged Logic. 39:1-39:31
- Hansika Weerasena
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey. 40:1-40:41
Volume 29, Number 3, May 2024
- Jinxin Dong
Detecting Adversarial Examples Utilizing Pixel Value Diversity. 41:1-41:12 - Fatemeh Serajeh-hassani
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes. 42:1-42:18 - Yunping Zhao, Sheng Ma
EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs. 43:1-43:28 - Aidong Zhao
D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. 44:1-44:25 - Irith Pomeranz
Reduced On-chip Storage of Seeds for Built-in Test Generation. 45:1-45:16 - Shailja Thakur
VeriGen: A Large Language Model for Verilog Code Generation. 46:1-46:31 - Yandong Luo
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices. 47:1-47:19 - Irith Pomeranz
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences. 48:1-48:13 - Ireneusz Brzozowski
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder. 49:1-49:22 - Md. Moshiur Rahman
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice. 50:1-50:18 - Renjian Pan
Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems. 51:1-51:22 - Govind Prasad
SEDONUT: A Single Event Double Node Upset Tolerant SRAM for Terrestrial Applications. 52:1-52:13 - Hongduo Liu
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs. 53:1-53:25 - Chunlin Li
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC. 54:1-54:29 - Hasini Witharana
Incremental Concolic Testing of Register-Transfer Level Designs. 55:1-55:23 - Bo Yang
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. 56:1-56:17 - Juming Xian
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning. 57:1-57:19 - S. Sivakumar
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers. 58:1-58:24
Volume 29, Number 4, 2024
- Xiang Zhao
Load Balanced PIM-Based Graph Processing. 1-22 - Lokesh Soni
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell. 1-13 - Hadi Esmaeilzadeh
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. 1-33 - Upma Gandhi
Applying reinforcement learning to learn best net to rip and re-route in global routing. 1-21 - Huan Tian
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement. 1-24 - Jan Spieck
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. 1-43 - Jian-De Li
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips. 1-27 - Zhisheng Chen
Capacity-Aware Wash Optimization with Dynamic Fluid Scheduling and Channel Storage for Continuous-Flow Microfluidic Biochips. 1-28 - Priyanka Joshi
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers. 1-32 - Ruobing Han
CuPBoP: Making CUDA a Portable Language. 1-25 - Cheng-Hsien Lin
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. 1-27 - Nan Wu
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect. 1-42 - Isaac McDaniel
Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of Functionality. 1-23
Volume 29, Number 5, 2024
- Wenyan Yan
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway. 1-28 - Rodolfo Jordão
IDeSyDe: Systematic Design Space Exploration via Design Space Identification. 1-45 - Chengtao Lai
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips. 1-20 - Rijoy Mukherjee
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis. 1-23 - Ganapati Bhat
Introduction to the Special Issue on Embedded System Software/Tools. 1-3 - Ping-Xiang Chen
ZoneTrace: Zone Monitoring Tool for F2FS on ZNS SSDs. 1-15 - Hongfei Wang
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies. 1-26 - Jiseung Kim
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning. 1-25 - Ehsan Aghapour
ARM-CO-UP: ARM COoperative Utilization of Processors. 1-30 - Peng Xu
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior. 1-22 - Aritra Bagchi
POEM: Performance Optimization and Endurance Management for Non-volatile Caches. 1-36 - Mengyu Liu
CPSim: Simulation Toolbox for Security Problems in Cyber-Physical Systems. 1-16 - Davide Baroffio
Enhanced Compiler Technology for Software-based Hardware Fault Detection. 1-23 - Devleena Ghosh
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together. 1-37 - Negar Aghapour Sabbagh
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification. 1-19 - Tinghuan Chen
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization. 1-23 - Chukwufumnanya Ogbogu
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators. 1-29 - Xiaoqian Wu
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm. 1-27 - Can Deng
Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming. 1-20 - Keerthi K.
FortiFix : A Fault Attack Aware Compiler Framework for Crypto Implementations. 1-18 - Changxu Liu
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication. 1-26
Volume 29, Number 6, 2024
- Wei-Hsiang Tseng
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits. 1-22 - Zhenyi Gao
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array. 1-23 - Kean Chen
Automatic Test Pattern Generation for Robust Quantum Circuit Testing. 1-36 - Arijit Nath
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories. 1-24 - Deepthi Amuru
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation. 1-33 - Ayush Dahiya
Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency. 1-15 - Danny Pereira
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach. 1-36 - Hongfei Wang
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling. 1-25 - Zhuoran Li
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis. 1-25 - Sahan Sanjaya
Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers. 1-22 - Jingui Lin
An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model. 1-16 - Wei-Kai Fang
Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs. 1-22 - Xiaoyu Sun
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. 1-27 - Chencan Zhou
A Robust Newton Iteration Method for Mixed-Cell-Height Circuit Legalization Under Technology and Region Constraints. 1-25
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