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Kevin J. M. Martin
Person information
- affiliation: University of Southern Brittany, France
- affiliation (PhD 2010): University of Rennes 1, France
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2020 – today
- 2024
- [j10]Chilankamol Sunny
, Satyajit Das
CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs. IEEE Trans. Parallel Distributed Syst. 35(7): 1293-1306 (2024) - [c32]Joseph W. Faye, Naouel Haggui
Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming Applications. DASIP 2024: 68-79 - [c31]Chilankamol Sunny
Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications. DASIP 2024: 83-95 - [c30]Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy:
SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs. DSD 2024: 242-249 - 2023
- [b2]Kevin J. M. Martin:
Mapping parallel applications on parallel architectures: Granularity of parallelism and synchronisation. University of Southern Brittany, France, 2023 - [j9]Satyajit Das
An Efficient and Flexible Stochastic CGRA Mapping Approach. ACM Trans. Embed. Comput. Syst. 22(1): 8:1-8:24 (2023) - 2022
- [j8]Mostafa Rizk
Run-Time Remapping Algorithm of Dataflow Actors on NoC-Based Heterogeneous MPSoCs. IEEE Trans. Parallel Distributed Syst. 33(10): 3959-3976 (2022) - [j7]Alemeh Ghasemi
The Impact of Cache and Dynamic Memory Management in Static Dataflow Applications. J. Signal Process. Syst. 94(7): 721-738 (2022) - [j6]Chilankamol Sunny
Energy Efficient Hardware Loop Based Optimization for CGRAs. J. Signal Process. Syst. 94(9): 895-912 (2022) - [c29]Marcelo Ruaro, Kevin J. M. Martin:
ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling. DroneSE/RAPIDO@HiPEAC 2022: 39-46 - [c28]Kevin J. M. Martin:
Twenty Years of Automated Methods for Mapping Applications on CGRA. IPDPS Workshops 2022: 679-686 - [c27]Navonil Chatterjee, Marcelo Ruaro, Kevin J. M. Martin, Jean-Philippe Diguet:
Mitigating Transceiver and Token Controller Permanent Faults in Wireless Network-on-Chip. PDP 2022: 238-245 - 2021
- [j5]Rodrigo Cataldo
Subutai: Speeding Up Legacy Parallel Applications Through Data Synchronization. IEEE Trans. Parallel Distributed Syst. 32(5): 1102-1116 (2021) - [j4]Rohit Prasad
Floating Point CGRA based Ultra-Low Power DSP Accelerator. J. Signal Process. Syst. 93(10): 1159-1171 (2021) - [c26]Chilankamol Sunny, Satyajit Das
Hardware Based Loop Optimization for CGRA Architectures. ARC 2021: 65-80 - [c25]Alemeh Ghasemi, Rodrigo Cataldo, Jean-Philippe Diguet, Kevin J. M. Martin
On Cache Limits for Dataflow Applications and Related Efficient Memory Management Strategies. DASIP 2021: 68-76 - 2020
- [c24]Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi:
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE 2020: 1067-1072 - [c23]Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy:
Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. ICASSP 2020: 1563-1567
2010 – 2019
- 2019
- [j3]Satyajit Das
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1095-1108 (2019) - [c22]Satyajit Das, Kevin J. M. Martin, Philippe Coussy:
Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs. DATE 2019: 336-341 - 2018
- [c21]Rodrigo Cataldo, Ramon Fernandes, Kevin J. M. Martin
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications. DAC 2018: 83:1-83:6 - [c20]Hugo Miomandre
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. PARMA-DITAM@HiPEAC 2018: 51-56 - [c19]Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi:
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. ISCAS 2018: 1-5 - [c18]Hemanta Kumar Mondal
Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing. SoCC 2018: 1-6 - 2017
- [j2]Thanh Dinh Ngo
Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs. J. Signal Process. Syst. 87(1): 63-80 (2017) - [c17]Satyajit Das
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. ASP-DAC 2017: 127-132 - [c16]Satyajit Das
A 142MOPS/mW integrated programmable array accelerator for smart visual processing. ISCAS 2017: 1-4 - 2016
- [c15]Kevin J. M. Martin
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation. DAC 2016: 35:1-35:6 - [c14]Pierre Langlois, Kevin J. M. Martin, Eduardo Juárez Martínez:
Demo Night. DASIP 2016: 222 - [c13]Satyajit Das
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI 2016: 655-660 - 2015
- [c12]Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva:
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. DASIP 2015: 1-2 - [c11]Paola Vallejo, Mickaël Kerboeuf, Kevin J. M. Martin, Jean-Philippe Babau:
Improving reuse by means of asymmetrical model migrations: An application to the Orcc case study. MoDELS 2015: 358-367 - 2014
- [c10]Thomas Peyret
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP 2014: 169-172 - [c9]Thanh Dinh Ngo
Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC. DASIP 2014: 1-8 - [c8]Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel
Orcc's compa-backend demonstration. DASIP 2014: 1-2 - [c7]Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet:
Virtual Devices for Hot-Pluggable Processors. DSD 2014: 58-65 - [c6]Thomas Peyret
An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI 2014: 229-230 - 2013
- [c5]Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet:
Virtual UARTs for Reconfigurable Multi-processor Architectures. IPDPS Workshops 2013: 252-259 - [c4]Antoine Floch, Tomofumi Yuki, Ali El Moussawi, Antoine Morvan, Kevin J. M. Martin, Maxime Naullet, Mythri Alle, Ludovic L'Hours, Nicolas Simon, Steven Derrien, François Charot, Christophe Wolinski, Olivier Sentieys:
GeCoS: A framework for prototyping custom hardware design flows. SCAM 2013: 100-105 - 2012
- [j1]Kevin J. M. Martin
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation. ACM Trans. Reconfigurable Technol. Syst. 5(2): 10:1-10:38 (2012) - 2010
- [b1]Kevin J. M. Martin:
Génération automatique d'extensions de jeux d'instructions de processeurs. (Automatic Generation of Instruction-set Extensions). University of Rennes 1, France, 2010
2000 – 2009
- 2009
- [c3]Kevin J. M. Martin
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. ASAP 2009: 145-152 - [c2]Christophe Wolinski, Krzysztof Kuchcinski, Kevin J. M. Martin, Erwan Raffin, François Charot:
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. ERSA 2009: 29-42 - [c1]Kevin J. M. Martin
Constraint-Driven Identification of Application Specific Instructions in the DURASE System. SAMOS 2009: 194-203
Coauthor Index
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last updated on 2024-11-20 21:55 CET by the dblp team
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