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Duckgyu Shin
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2020 – today
- 2024
- [j6]Naoya Onizawa
, Ryoma Sasaki, Duckgyu Shin
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12: 102050-102060 (2024) - 2023
- [j5]Duckgyu Shin
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 108-118 (2023) - [j4]Naoya Onizawa
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34(12): 10999-11005 (2023) - [c4]Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT 2023: 274-275 - [c3]Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS 2023: 1-4 - [i2]Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR abs/2302.12454 (2023) - [i1]Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu:
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR abs/2304.11839 (2023) - 2022
- [j3]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9(3): 653-674 (2022) - [c2]Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 2022: 1-4 - 2020
- [j2]Duckgyu Shin
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8: 188004-188014 (2020) - [j1]Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu:
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7(1): 41-58 (2020)
2010 – 2019
- 2019
- [c1]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS 2019: 115-116
Coauthor Index
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