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Xiulong Wu
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2020 – today
- 2024
- [j60]Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng
, Xiulong Wu:
A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations. Microelectron. J. 144: 106087 (2024) - [j59]Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng
A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC. Microelectron. J. 145: 106124 (2024) - [j58]Yue Zhao
Configurable in-memory computing architecture based on dual-port SRAM. Microelectron. J. 147: 106163 (2024) - [j57]Zhiting Lin, Changxin Yue
Cross-coupled 4T2R multi-logic in-memory computing circuit design. Microelectron. J. 147: 106179 (2024) - [j56]Chunyu Peng
High energy efficient and configurable CIM macro for image processing. Microelectron. J. 148: 106212 (2024) - [j55]Shiyu Zhao
Design of polarity hardening SRAM for mitigating single event multiple node upsets. Microelectron. J. 149: 106214 (2024) - [j54]Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng
An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. Microelectron. J. 151: 106308 (2024) - [j53]Zhiting Lin, Runru Yu
A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC. Microelectron. J. 153: 106397 (2024) - [j52]Qiang Zhao
An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor. Microelectron. J. 154: 106444 (2024) - [j51]Chunyu Peng
High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 60(5): 6550-6561 (2024) - [j50]Yongliang Zhou
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 187-200 (2024) - [j49]Zhongzhen Tong
A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 606-619 (2024) - [j48]Jin Zhang
A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3658-3671 (2024) - [j47]Yongliang Zhou
Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4019-4031 (2024) - [j46]Li Liu
Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1759-1763 (2024) - [j45]Jiaxing Sun, Shichao Jin
A 2.77-dB NF K-Band Four-Element Dual-Beam Phased-Array Receiver With 39-dB Tx-Band Rejection for SATCOM Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2991-2995 (2024) - [j44]Licai Hao
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 597-608 (2024) - [j43]Licai Hao, Yaling Wang
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024) - [c10]Zhiting Lin, Yunlong Liu, Yaling Wang, Yue Zhao, Chunyu Peng, Xiulong Wu:
SRAM-Based Digital CIM Macro for Linear Interpolation and MAC. ISCAS 2024: 1-5 - [c9]Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu:
A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. ISCAS 2024: 1-5 - 2023
- [j42]Licai Hao, Bin Qiang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Li Liu, Qiang Zhao, Xiulong Wu, Fei Sun:
Radiation-hardened 14T SRAM cell by polar design for space applications. IEICE Electron. Express 20(13): 20230083 (2023) - [j41]Qiang Zhao
Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments. Int. J. Circuit Theory Appl. 51(1): 398-409 (2023) - [j40]Zhiting Lin
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. IEEE J. Solid State Circuits 58(5): 1472-1486 (2023) - [j39]Licai Hao, Li Liu, Qi Shi, Bin Qiang, Zhengya Li, Nianlong Liu, Chenghu Dai, Qiang Zhao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu:
Design of radiation-hardened memory cell by polar design for space applications. Microelectron. J. 132: 105691 (2023) - [j38]Chenghu Dai, Yuanyuan Du, Qi Shi, Ruixuan Wang, Hao Zheng, Wenjuan Lu, Chunyu Peng, Licai Hao, Zhiting Lin, Xiulong Wu:
Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design. Microelectron. J. 132: 105699 (2023) - [j37]Pengfei Li, Xiuying Wang, Yin Zhang, Haoyu Wang, Jianjie Lu, Qiang Zhao
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology. Microelectron. J. 141: 105954 (2023) - [j36]Zuheng Wu
Threshold Switching Memristor-Based Voltage Regulative Circuit. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1034-1038 (2023) - [j35]Zhiting Lin
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 522-531 (2023) - [j34]Zhiting Lin
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 776-788 (2023) - [j33]Zhongzhen Tong
In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1454-1458 (2023) - [c8]Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. ESSDERC 2023: 13-16 - 2022
- [j32]Xulei Wu, Bingjie Dang, Hong Wang, Xiulong Wu, Yuchao Yang
Spike-Enabled Audio Learning in Multilevel Synaptic Memristor Array-Based Spiking Neural Network. Adv. Intell. Syst. 4(3) (2022) - [j31]Qiang Zhao
Novel radiation-hardened latch design for space-radiation environments. IEICE Electron. Express 19(13): 20220170 (2022) - [j30]Yue Zhao
An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset. Microelectron. J. 128: 105578 (2022) - [j29]Jin Zhang
In-Memory Multibit Multiplication Based on Bitline Shifting. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 354-358 (2022) - [j28]Pei Huang
Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2011-2015 (2022) - [j27]Yue Zhao
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 566-578 (2022) - 2021
- [j26]Zhiting Lin
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. IEEE J. Solid State Circuits 56(8): 2550-2562 (2021) - [j25]Zhiting Lin
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. IEEE J. Solid State Circuits 56(9): 2832-2844 (2021) - [j24]Chunyu Peng
Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 466-470 (2021) - [j23]Zhiting Lin
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2628-2632 (2021) - 2020
- [j22]Wenjuan Lu, Guoying Qin, Zhiting Lin, Xiulong Wu, Chunyu Peng:
A new reading mode based on balanced pre-charging and group decoding. IEICE Electron. Express 17(24): 20200360 (2020) - [j21]Jinkai Wang, Chenyu Lian, Yining Bai
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. 67-I(12): 4247-4258 (2020) - [j20]Zhiting Lin
Challenges and Solutions of the TFET Circuit Design. IEEE Trans. Circuits Syst. 67-I(12): 4918-4931 (2020) - [j19]Zhiting Lin
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 607-619 (2020) - [j18]Qiang Zhao
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 848-852 (2020) - [j17]Zhiting Lin
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1316-1320 (2020) - [c7]Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. DAC 2020: 1-6 - [c6]Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. ISSCC 2020: 232-234
2010 – 2019
- 2019
- [j16]Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
An inverter chain with parallel output nodes for eliminating single-event transient pulse. IEICE Electron. Express 16(4): 20181118 (2019) - [j15]Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A single event upset tolerant latch with parallel nodes. IEICE Electron. Express 16(11): 20190208 (2019) - [j14]Qiang Zhao
Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS. IEICE Electron. Express 16(17): 20190407 (2019) - [j13]Xiaoqing Zhao
Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 226-238 (2019) - [j12]Chunyu Peng
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 407-415 (2019) - [c5]Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao:
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM. NANOARCH 2019: 1-6 - 2018
- [j11]Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng:
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. IEICE Electron. Express 15(10): 20180332 (2018) - [j10]Jingfeng Liu, Quan Li, Xin Liu, Zhiqiang Li, Yu Liu, Zhiting Lin, Xiulong Wu:
Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system. IEICE Electron. Express 15(11): 20180372 (2018) - [j9]Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu:
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. IEICE Electron. Express 15(15): 20180604 (2018) - [j8]Chunyu Peng
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 584-588 (2018) - 2017
- [j7]Chunyu Peng, Ziyang Chen, Jingbo Zhang, Songsong Xiao, Changyong Liu, Xiulong Wu, Zhiting Lin:
A radiation harden enhanced Quatro (RHEQ) SRAM cell. IEICE Electron. Express 14(18): 20170784 (2017) - [j6]Zhiting Lin
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process. IEEE J. Solid State Circuits 52(3): 669-677 (2017) - 2016
- [j5]Minghua Li, Guanming Huang, Xiulong Wu, Liuxi Qian, Xuan Zeng, Dian Zhou:
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. Sci. China Inf. Sci. 59(8): 082401:1-082401:16 (2016) - [j4]Chunyu Peng, Lijun Guan, Wenjuan Lu, Xiulong Wu, Xincun Ji:
Read/write margin enhanced 10T SRAM for low voltage application. IEICE Electron. Express 13(12): 20160382 (2016) - [j3]Chunyu Peng, Xiangwen An, Zhiting Lin, Xiulong Wu, Wei Hong:
Additive-calibration scheme for leakage compensation of low voltage SRAM. IEICE Electron. Express 13(18): 20160720 (2016) - 2015
- [j2]Zhiting Lin, Xiulong Wu:
Analyzing and modeling mobility for infrastructure-less communication. J. Netw. Comput. Appl. 53: 156-163 (2015) - [c4]Zhiting Lin, Chunyu Peng, Xiulong Wu, Xiufang Jiang:
Human dynamics in mobile social networks: A study of inter-node relationships. FSKD 2015: 806-810 - 2013
- [j1]Xiulong Wu, Minghua Li, Zhiting Lin, Mengyuan Xi, Junning Chen:
The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip. Sensors 13(7): 8771-8785 (2013) - 2012
- [c3]Ruixing Lu, Na Bai, Baitao Lv, Jiafeng Zhu, Xiulong Wu:
Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design. NAS 2012: 109-113 - 2011
- [c2]Chen Hu, Jun Yang, Meng Zhang, Xiulong Wu:
A 12T Subthreshold SRAM Bit-Cell for Medical Device Application. CyberC 2011: 540-543
2000 – 2009
- 2006
- [c1]Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu:
A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design. APCCAS 2006: 1465-1468
Coauthor Index
Zhi-Ting Lin
aka: Zhiting Lin
aka: Zhiting Lin
[j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [j47] [j46] [j44] [j43] [c10] [c9] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [c8] [j31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j12] [j11] [j9] [j8] [j7] [j6] [j4] [j3] [c4]
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last updated on 2024-12-15 02:17 CET by the dblp team
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