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Samuel Nascimento Pagliarini
Samuel N. Pagliarini – Samuel Pagliarini
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- affiliation: Carnegie Mellon University, Pittsburgh, PA, USA
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2020 – today
- 2025
- [j31]Johann Knechtel, Mohammad Eslami
, Peng Zou, Min Wei, Xingyu Tong
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2025(1): 37-77 (2025) - [j30]Felipe Almeida
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1348-1360 (2025) - [c42]Zain Ul Abideen, Levent Aksoy, Samuel Pagliarini:
Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure? DATE 2025: 1-2 - 2024
- [j29]Zain Ul Abideen
An Overview of FPGA-inspired Obfuscation Techniques. ACM Comput. Surv. 56(12): 299:1-299:35 (2024) - [j28]Zain Ul Abideen
Impact of Orientation on the Bias of SRAM-Based PUFs. IEEE Des. Test 41(3): 14-20 (2024) - [j27]Malik Imran
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography. IEEE Embed. Syst. Lett. 16(4): 485-488 (2024) - [j26]Muayad J. Aljafar, Zain Ul Abideen
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators. IEEE Embed. Syst. Lett. 16(4): 493-496 (2024) - [j25]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing layout effects for analog logic locking. J. Cryptogr. Eng. 14(2): 311-324 (2024) - [j24]Mohammad Eslami
SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans. IEEE Trans. Computers 73(12): 2761-2775 (2024) - [j23]Malik Imran
High-Speed Design of Post Quantum Cryptography With Optimized Hashing and Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 847-851 (2024) - [c41]Samuel Pagliarini
REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography. AsiaCCS 2024 - [c40]Levent Aksoy, Debapriya Basu Roy, Malik Imran
Multiplierless Design of High-Speed Very Large Constant Multiplications. ASPDAC 2024: 957-962 - [c39]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. DATE 2024: 1-6 - [c38]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. LATS 2024: 1-6 - [i41]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing Layout Effects for Analog Logic Locking. CoRR abs/2401.06508 (2024) - [i40]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. CoRR abs/2401.07142 (2024) - [i39]Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini:
SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans. CoRR abs/2402.12162 (2024) - [i38]Samuel Pagliarini, Aikata, Malik Imran, Sujoy Sinha Roy:
REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography. CoRR abs/2403.09352 (2024) - [i37]Muayad J. Aljafar, Zain Ul Abideen, Adriaan Peetermans, Benedikt Gierlichs, Samuel Pagliarini:
SCALLER: Standard Cell Assembled and Local Layout Effect-based Ring Oscillators. CoRR abs/2406.01258 (2024) - [i36]Felipe Almeida, Levent Aksoy, Samuel Pagliarini:
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. CoRR abs/2409.16959 (2024) - [i35]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [j22]Malik Imran
High-speed SABER key encapsulation mechanism in 65nm CMOS. J. Cryptogr. Eng. 13(4): 461-471 (2023) - [j21]Malik Imran
A Versatile and Flexible Multiplier Generator for Large Integer Polynomials. J. Hardw. Syst. Secur. 7(2): 55-71 (2023) - [j20]Tiago D. Perez
Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2094-2107 (2023) - [j19]Zain Ul Abideen
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3157-3170 (2023) - [j18]Aikata
KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 747-758 (2023) - [j17]Levent Aksoy
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 812-825 (2023) - [c37]Mohammad Eslami
Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. ISPD 2023: 256-264 - [c36]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis
Resynthesis-based Attacks Against Logic Locking. ISQED 2023: 1-8 - [i34]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis
Resynthesis-based Attacks Against Logic Locking. CoRR abs/2301.04400 (2023) - [i33]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis
Hybrid Protection of Digital FIR Filters. CoRR abs/2301.11115 (2023) - [i32]Zain Ul Abideen, Sumathi Gokulanathan, Muayad J. Aljafar, Samuel Pagliarini:
An Overview of FPGA-inspired Obfuscation Techniques. CoRR abs/2305.15999 (2023) - [i31]Mohammad Eslami, Tiago D. Perez, Samuel Pagliarini:
SALSy: Security-Aware Layout Synthesis. CoRR abs/2308.06201 (2023) - [i30]Zain Ul Abideen, Rui Wang, Tiago Diadami Perez, Geert Jan Schrijen, Samuel Pagliarini:
Impact of Orientation on the Bias of SRAM-Based PUFs. CoRR abs/2308.06730 (2023) - [i29]Levent Aksoy, Debapriya Basu Roy, Malik Imran, Samuel Pagliarini:
Multiplierless Design of High-Speed Very Large Constant Multiplications. CoRR abs/2309.05550 (2023) - [i28]Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. CoRR abs/2311.05982 (2023) - [i27]Malik Imran, Aikata, Sujoy Sinha Roy, Samuel N. Pagliarini:
Towards High-speed ASIC Implementations of Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2023: 716 (2023) - 2022
- [j16]Felipe Almeida
Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study. IEEE Access 10: 44827-44839 (2022) - [j15]Levent Aksoy
Multiplierless Design of Very Large Constant Multiplications in Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4503-4507 (2022) - [c35]Tiago D. Perez, Samuel Pagliarini:
A Side-Channel Hardware Trojan in 65nm CMOS with 2μW precision and Multi-bit Leakage Capability. ASP-DAC 2022: 9-10 - [c34]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Leveraging Layout-based Effects for Locking Analog ICs. ASHES@CCS 2022: 5-13 - [c33]Tiago D. Perez, Marcio M. Gonçalves, Leonardo Gobatto, Marcelo Brandalero, José Rodrigo Azambuja, Samuel Pagliarini:
G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators. DATE 2022: 544-547 - [c32]Levent Aksoy, Alexander Hepp, Johanna Baehr
Hardware Obfuscation of Digital FIR Filters. DDECS 2022: 68-73 - [c31]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. ICCAD 2022: 69:1-69:9 - [c30]Mohammad Eslami
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection. ISQED 2022: 1-6 - [c29]Mahdieh Grailoo, Mairo Leier, Samuel Pagliarini:
Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks. ISQED 2022: 1-6 - [c28]Giorgi Basiashvili
Obfuscating the Hierarchy of a Digital IP. SAMOS 2022: 303-314 - [i26]Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini:
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection. CoRR abs/2201.01130 (2022) - [i25]Levent Aksoy, Alexander Hepp, Johanna Baehr, Samuel Pagliarini:
Hardware Obfuscation of Digital FIR Filters. CoRR abs/2202.10022 (2022) - [i24]Mahdieh Grailoo, Zain Ul Abideen
Preventing Distillation-based Attacks on Neural Network IP. CoRR abs/2204.00292 (2022) - [i23]Giorgi Basiashvili, Zain Ul Abideen, Samuel Pagliarini:
Obfuscating the Hierarchy of a Digital IP. CoRR abs/2205.09892 (2022) - [i22]Levent Aksoy, Debapriya Basu Roy, Malik Imran, Patrick Karl
Multiplierless Design of Very Large Constant Multiplications in Cryptography. CoRR abs/2205.10591 (2022) - [i21]Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini:
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. CoRR abs/2207.05413 (2022) - [i20]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl:
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. CoRR abs/2208.09235 (2022) - [i19]Muayad J. Aljafar
Leveraging Layout-based Effects for Locking Analog ICs. CoRR abs/2209.01856 (2022) - [i18]Malik Imran, Felipe Almeida, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
High-speed SABER Key Encapsulation Mechanism in 65nm CMOS. IACR Cryptol. ePrint Arch. 2022: 530 (2022) - [i17]Aikata, Ahmet Can Mert, Malik Imran, Samuel Pagliarini, Sujoy Sinha Roy:
KaLi: A Crystal for Post-Quantum Security. IACR Cryptol. ePrint Arch. 2022: 1086 (2022) - 2021
- [j14]Samuel Pagliarini
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38(4): 109-118 (2021) - [c27]Zain Ul Abideen
From FPGAs to Obfuscated eASICs: Design and Security Trade-offs. AsianHOST 2021: 1-4 - [c26]Felipe Almeida, Levent Aksoy
Side-Channel Attacks on Triple Modular Redundancy Schemes. ATS 2021: 79-84 - [c25]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. ASHES@CCS 2021: 85-90 - [c24]Malik Imran
An Open-source Library of Large Integer Polynomial Multipliers. DDECS 2021: 145-150 - [c23]Levent Aksoy
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS 2021: 1-7 - [c22]Tiago D. Perez, Malik Imran
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. ISCAS 2021: 1-5 - [c21]Mateus Saquetti, Raphael Martins Brum, Bruno Zatt, Samuel Pagliarini, Weverton Cordeiro, José Rodrigo Azambuja:
A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization. ISVLSI 2021: 73-78 - [c20]Samuel Pagliarini:
A Tutorial on Design Obfuscation: from Transistors to Systems. LATS 2021: 1-3 - [i16]Malik Imran, Zain Ul Abideen, Samuel Pagliarini:
An Open-source Library of Large Integer Polynomial Multipliers. CoRR abs/2101.11404 (2021) - [i15]Tiago D. Perez, Malik Imran, Pablo Vaz, Samuel Pagliarini:
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. CoRR abs/2102.00724 (2021) - [i14]Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini:
Side-Channel Attacks on Triple Modular Redundancy Schemes. CoRR abs/2104.04334 (2021) - [i13]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR abs/2105.06122 (2021) - [i12]Mateus Saquetti, Raphael Martins Brum, Bruno Zatt, Samuel Pagliarini, Weverton Cordeiro, José Rodrigo Azambuja:
A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization. CoRR abs/2105.09696 (2021) - [i11]Samuel Pagliarini:
A Tutorial on Design Obfuscation: from Transistors to Systems. CoRR abs/2108.11335 (2021) - [i10]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. CoRR abs/2109.07824 (2021) - [i9]Zain Ul Abideen, Tiago Diadami Perez, Samuel Pagliarini:
From FPGAs to Obfuscated eASICs: Design and Security Trade-offs. CoRR abs/2110.05335 (2021) - [i8]Tiago Diadami Perez, Marcio M. Gonçalves, José Rodrigo Azambuja, Leonardo Gobatto, Marcelo Brandalero, Samuel Pagliarini:
G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators. CoRR abs/2111.06166 (2021) - [i7]Tiago D. Perez, Samuel Pagliarini:
Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration. CoRR abs/2112.02972 (2021) - [i6]Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini:
Design Space Exploration of SABER in 65nm ASIC. IACR Cryptol. ePrint Arch. 2021: 1202 (2021) - 2020
- [j13]Tiago D. Perez
A Survey on Split Manufacturing: Attacks, Defenses, and Challenges. IEEE Access 8: 184013-184035 (2020) - [j12]Mayler G. A. Martins
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 520-532 (2020) - [j11]Samuel N. Pagliarini
A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 31(4): 1113-1123 (2020) - [j10]Mehmet Meric Isgenc
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 585-595 (2020) - [c19]Giorgio Di Natale, Francesco Regazzoni
Latest Trends in Hardware Security and Privacy. DFT 2020: 1-4 - [c18]Farimah Farahmandi, Ozgur Sinanoglu
Design Obfuscation versus Test. ETS 2020: 1-10 - [c17]Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini
Latch-Based Logic Locking. HOST 2020: 132-141 - [c16]Malik Imran
An Area Aware Accelerator for Elliptic Curve Point Multiplication. ICECS 2020: 1-4 - [i5]Joseph Sweeney, Samuel Pagliarini, Lawrence T. Pileggi
Securing Digital Systems via Split-Chip Obfuscation. CoRR abs/2005.10083 (2020) - [i4]Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi
Latch-Based Logic Locking. CoRR abs/2005.10649 (2020) - [i3]Tiago D. Perez, Samuel Pagliarini:
A Survey on Split Manufacturing: Attacks, Defenses, and Challenges. CoRR abs/2006.04627 (2020) - [i2]Malik Imran
A Systematic Study of Lattice-based NIST PQC Algorithms: from Reference Implementations to Hardware Accelerators. CoRR abs/2009.07091 (2020) - [i1]Malik Imran, Samuel Pagliarini, Muhammad Rashid:
An Area Aware Accelerator for Elliptic Curve Point Multiplication. IACR Cryptol. ePrint Arch. 2020: 1148 (2020)
2010 – 2019
- 2019
- [j9]Ioannis Karageorgos
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. J. Hardw. Syst. Secur. 3(4): 382-396 (2019) - 2018
- [j8]Samuel N. Pagliarini
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1627-1636 (2018) - [c15]Thomas C. Jackson, Samuel Pagliarini
An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. ICRC 2018: 1-7 - 2017
- [j7]Rajat Subhra Chakraborty
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis. IEEE Trans. Emerg. Top. Comput. 5(2): 260-270 (2017) - [j6]Mohamad Imran Bin Bandan
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits. IEEE Trans. Reliab. 66(1): 233-244 (2017) - [c14]Samuel Pagliarini
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED 2017: 93-98 - [c13]Mehmet Meric Isgenc, Samuel Pagliarini
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. ISQED 2017: 180-185 - [c12]Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. NANOARCH 2017: 147-152 - 2014
- [j5]Luo Sun, Jimson Mathew, Samuel N. Pagliarini
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems. J. Low Power Electron. 10(3): 467-478 (2014) - [c11]Ioannis Sourdis, Christos Strydis
DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs. ARC 2014: 312-317 - [c10]Samuel N. Pagliarini
A placement strategy for reducing the effects of multiple faults in digital circuits. IOLTS 2014: 69-74 - [c9]Samuel N. Pagliarini
A hybrid reliability assessment method and its support of sequential logic modelling. IOLTS 2014: 182-183 - 2013
- [j4]Arwa Ben Dhia, Samuel N. Pagliarini
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectron. Reliab. 53(9-11): 1189-1193 (2013) - [j3]Samuel N. Pagliarini
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. Microelectron. Reliab. 53(9-11): 1230-1234 (2013) - [c8]Samuel N. Pagliarini
Single event transient mitigation through pulse quenching: Effectiveness at circuit level. ICECS 2013: 121-124 - [c7]Samuel N. Pagliarini
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. MWSCAS 2013: 113-116 - [c6]Samuel N. Pagliarini
Selective hardening against multiple faults employing a net-based reliability analysis. NEWCAS 2013: 1-4 - 2012
- [j2]Samuel N. Pagliarini
Exploring the feasibility of selective hardening for combinational logic. Microelectron. Reliab. 52(9-10): 1843-1847 (2012) - [c5]Samuel N. Pagliarini
Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. ICECS 2012: 753-756 - [c4]Samuel Nascimento Pagliarini
Selective hardening methodology for combinational logic. LATW 2012: 1-6 - 2011
- [b1]Samuel Nascimento Pagliarini:
VEasy: a tool suite towards the functional verification challenges. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2011 - [j1]José Rodrigo Azambuja, Samuel Pagliarini
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage. J. Electron. Test. 27(4): 541-550 (2011) - [c3]Samuel Nascimento Pagliarini
Evaluating coverage collection using the VEasy functional verification tool suite. LATW 2011: 1-6 - [c2]Samuel Nascimento Pagliarini
VEasy: A tool suite for teaching VLSI functional verification. MSE 2011: 94-97 - [c1]José Rodrigo Azambuja, Samuel Pagliarini
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. SBCCI 2011: 161-166
Coauthor Index
Lirida A. B. Naviner
aka: Lirida Alves de Barros Naviner
aka: Lirida Alves de Barros Naviner
Tiago D. Perez
aka: Tiago Diadami Perez
aka: Tiago Diadami Perez
Lawrence T. Pileggi
aka: Larry T. Pileggi
aka: Larry T. Pileggi
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