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Evangeline F. Y. Young
F. Y. Young – Fung Yu Young – Evan F. Y. Young
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- affiliation: Chinese University of Hong Kong
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2020 – today
- 2024
- [j63]Evangeline F. Y. Young
:
Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023). IEEE Des. Test 41(2): 88-89 (2024) - [j62]Fangzhou Wang
FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1566-1579 (2024) - [j61]Lixin Liu
Xplace: An Extremely Fast and Extensible Placement Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1872-1885 (2024) - [j60]Lixin Liu
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2426-2439 (2024) - [c134]Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young:
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. ASPDAC 2024: 65-70 - [c133]Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC 2024: 392-397 - [c132]Qin Luo
A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. FCCM 2024: 1-7 - [c131]Xinshi Zang
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. ACM Great Lakes Symposium on VLSI 2024: 164-169 - [c130]Tianji Liu
On Advanced Methodologies for Microarchitecture Design Space Exploration. ACM Great Lakes Symposium on VLSI 2024: 376-382 - [c129]Qijing Wang
A Multi-agent Generative Model for Collaborative Global Routing Refinement. ACM Great Lakes Symposium on VLSI 2024: 383-389 - [c128]Xinshi Zang
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. ACM Great Lakes Symposium on VLSI 2024: 433-439 - [c127]Qijing Wang
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation. ACM Great Lakes Symposium on VLSI 2024: 511-515 - [c126]Evangeline F. Y. Young
Accelerating Physical Design from 1 to N. ISPD 2024: 227 - [i7]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i6]Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel:
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR abs/2405.05590 (2024) - [i5]Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young:
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. CoRR abs/2407.00009 (2024) - [i4]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [j59]Jingsong Chen
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 164-177 (2023) - [j58]Shiju Lin
GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 583-593 (2023) - [j57]Bentian Jiang
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3067-3077 (2023) - [c125]Dan Zheng, Evangeline F. Y. Young:
An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. ASP-DAC 2023: 522-528 - [c124]Jinwei Liu, Evangeline F. Y. Young:
EDGE: Efficient DAG-based Global Routing Engine. DAC 2023: 1-6 - [c123]Tianji Liu, Evangeline F. Y. Young:
Rethinking AIG Resynthesis in Parallel. DAC 2023: 1-6 - [c122]Xinshi Zang
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI 2023: 357-361 - [c121]Xinshi Zang
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI 2023: 593-598 - [c120]Fangzhou Wang
FastPass: Fast Pin Access Analysis with Incremental SAT Solving. ISPD 2023: 9-16 - [c119]Evangeline F. Y. Young
GPU Acceleration in Physical Synthesis. ISPD 2023: 167 - [c118]Fangzhou Wang
Security Closure of IC Layouts Against Hardware Trojans. ISPD 2023: 229-237 - 2022
- [j56]Haocheng Li
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 143-154 (2022) - [j55]Bentian Jiang
CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1888-1901 (2022) - [j54]Bentian Jiang
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2671-2684 (2022) - [c117]Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong
NovelRewrite: node-level parallel AIG rewriting. DAC 2022: 427-432 - [c116]Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong
Partition and place finite element model on wafer-scale engine. DAC 2022: 631-636 - [c115]Qijing Wang
A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC 2022: 967-972 - [c114]Lixin Liu
Xplace: an extremely fast and extensible global placement framework. DAC 2022: 1309-1314 - [c113]Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. ISPD 2022: 185-192 - [c112]Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. ITC 2022: 100-107 - [e3]Tulika Mitra, Evangeline F. Y. Young, Jinjun Xiong:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022. ACM 2022, ISBN 978-1-4503-9217-4 [contents] - [i3]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. CoRR abs/2211.07997 (2022) - 2021
- [j53]Haocheng Li
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1995-2008 (2021) - [c111]Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young:
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC 2021: 176-182 - [c110]Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. ASP-DAC 2021: 885-891 - [c109]Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young:
Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. DAC 2021: 169-174 - [c108]Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young:
REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. DAC 2021: 1135-1140 - [c107]Bentian Jiang, Xiaopeng Zhang, Lixin Liu
Building up End-to-end Mask Optimization Framework with Self-training. ISPD 2021: 63-70 - 2020
- [j52]Gengjie Chen
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1217-1230 (2020) - [j51]Peishan Tu
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1245-1257 (2020) - [j50]Gengjie Chen
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1902-1915 (2020) - [j49]Haoyu Yang
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2822-2834 (2020) - [j48]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. 25(2): 21:1-21:23 (2020) - [j47]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. ACM Trans. Design Autom. Electr. Syst. 25(5): 48:1-48:31 (2020) - [c106]Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young:
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC 2020: 1-6 - [c105]Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young:
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. ICCAD 2020: 17:1-17:8 - [c104]Bentian Jiang, Lixin Liu
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD 2020: 20:1-20:9 - [c103]Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young:
Layout Pattern Generation and Legalization with Generative Learning Models. ICCAD 2020: 32:1-32:9 - [c102]Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu
CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. ICCAD 2020: 142:1-142:9 - [i2]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR abs/2007.03989 (2020)
2010 – 2019
- 2019
- [j46]Haoyu Yang
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1175-1187 (2019) - [j45]Jian Kuang
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1731-1743 (2019) - [j44]Ilgweon Kang
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. 24(1): 13:1-13:33 (2019) - [c101]Bentian Jiang, Hang Zhang
A fast machine learning-based mask printability predictor for OPC acceleration. ASP-DAC 2019: 412-419 - [c100]Gengjie Chen, Chak-Wa Pui, Haocheng Li
Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC 2019: 754-760 - [c99]Haocheng Li, Satwik Patnaik
Attacking Split Manufacturing from a Deep Learning Perspective. DAC 2019: 135 - [c98]Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young:
MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. DAC 2019: 216 - [c97]Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu:
FIT: Fill Insertion Considering Timing. DAC 2019: 221 - [c96]Gengjie Chen, Evangeline F. Y. Young:
Dim Sum: Light Clock Tree by Small Diameter Sum. DATE 2019: 174-179 - [c95]Haocheng Li
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. ICCAD 2019: 1-7 - [c94]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD 2019: 1-8 - [c93]Evangeline F. Y. Young:
Session details: Patterning and Machine Learning. ISPD 2019 - [c92]Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young:
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP 2019: 1-8 - [i1]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. CoRR abs/1906.10773 (2019) - 2018
- [j43]Jian Kuang
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1251-1264 (2018) - [j42]Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2022-2035 (2018) - [j41]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2036-2049 (2018) - [c91]Chak-Wa Pui, Peishan Tu, Haocheng Li
A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC 2018: 592-598 - [c90]Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: mask optimization with lithography-guided generative adversarial nets. DAC 2018: 131:1-131:6 - [c89]Haocheng Li
Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC 2018: 150:1-150:6 - [c88]Steve Dai, Yuan Zhou, Hang Zhang
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM 2018: 129-132 - [c87]Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young:
Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI 2018: 261-266 - 2017
- [c86]Jian Kuang, Evangeline F. Y. Young:
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. DAC 2017: 61:1-61:6 - [c85]Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. DAC 2017: 62:1-62:6 - [c84]Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. DAC 2017: 70:1-70:6 - [c83]Gengjie Chen, Peishan Tu, Evangeline F. Y. Young:
SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. ICCAD 2017: 569-576 - [c82]Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936 - [c81]Hang Zhang
Bilinear Lithography Hotspot Detection. ISPD 2017: 7-14 - [c80]Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young:
Fence-aware detailed-routability driven placement. SLIP 2017: 1-7 - [c79]Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young:
Timing driven routing tree construction. SLIP 2017: 1-8 - [c78]Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young:
Lithography hotspot detection: From shallow to deep learning. SoCC 2017: 233-238 - 2016
- [j40]Jian Kuang, Evangeline F. Y. Young:
Row-structure stencil planning approaches for E-beam lithography with overlapped characters. Integr. 55: 232-245 (2016) - [j39]Wing-Kai Chow, Evangeline F. Y. Young:
Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. 9: 2-12 (2016) - [j38]Evangeline F. Y. Young, Azadeh Davoodi:
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. 21(3): 36:1 (2016) - [j37]Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young:
An Effective Chemical Mechanical Polishing Fill Insertion Approach. ACM Trans. Design Autom. Electr. Syst. 21(3): 54:1-54:21 (2016) - [j36]Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young:
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 22(1): 10:1-10:26 (2016) - [j35]Jian Kuang
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1319-1332 (2016) - [c77]Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham:
3D floorplan representations: Corner links and partial order. 3DIC 2016: 1-5 - [c76]Hang Zhang
VLSI layout hotspot detection based on discriminative feature extraction. APCCAS 2016: 542-545 - [c75]Jian Kuang, Junjie Ye
Simultaneous template optimization and mask assignment for DSA with multiple patterning. ASP-DAC 2016: 75-82 - [c74]Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young:
Legalization algorithm for multiple-row height standard cell design. DAC 2016: 83:1-83:6 - [c73]Jian Kuang, Evangeline F. Y. Young:
Optimization for Multiple Patterning Lithography with cutting process and beyond. DATE 2016: 43-48 - [c72]Hang Zhang
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. ICCAD 2016: 47 - [c71]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
Incorporating cut redistribution with mask assignment to enable 1D gridded design. ICCAD 2016: 48 - [c70]Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD 2016: 67 - [e2]Evangeline F. Y. Young, Mustafa Ozdal:
Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016. ACM 2016, ISBN 978-1-4503-4039-7 [contents] - [r4]Evangeline F. Y. Young:
Slicing Floorplan Orientation. Encyclopedia of Algorithms 2016: 2002-2006 - 2015
- [j34]Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Planning Massive Interconnects in 3-D Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1808-1821 (2015) - [c69]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
A robust approach for process variation aware mask optimization. DATE 2015: 1591-1594 - [c68]Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young:
An effective triple patterning aware grid-based detailed routing approach. DATE 2015: 1641-1646 - [c67]Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young:
An Effective Chemical Mechanical Polishing Filling Approach. ISVLSI 2015: 44-49 - [e1]Azadeh Davoodi, Evangeline F. Y. Young:
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015. ACM 2015, ISBN 978-1-4503-3399-3 [contents] - 2014
- [j33]Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. Integr. 47(1): 105-114 (2014) - [c66]Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Structural planning of 3D-IC interconnects by block alignment. ASP-DAC 2014: 53-60 - [c65]Jackson H. C. Yeung, Evangeline F. Y. Young:
General purpose cross-referencing Microfluidic Biochip with reduced pin-count. ASP-DAC 2014: 238-243 - [c64]Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young:
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). FPGA 2014: 242 - [c63]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
Triple patterning lithography aware optimization for standard cell based design. ICCAD 2014: 108-115 - [c62]Jian Kuang, Evangeline F. Y. Young:
Overlapping-aware throughput-driven stencil planning for E-beam lithography. ICCAD 2014: 254-261 - [c61]Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy:
Reducing pin count on cross-referencing Digital Microfluidic Biochip. ISCAS 2014: 790-793 - [c60]Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young:
Cell density-driven detailed placement with displacement constraint. ISPD 2014: 3-10 - [c59]Jian Kuang, Evangeline F. Y. Young:
A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters. ISPD 2014: 109-116 - [c58]Wenzan Cai, Evangeline F. Y. Young:
A Fast Hypergraph Bipartitioning Algorithm. ISVLSI 2014: 607-612 - 2013
- [j32]Junjie Xiong, Yangfan Zhou, Michael R. Lyu, Evan F. Y. Young:
MDiag: Mobility-assisted diagnosis for wireless sensor networks. J. Netw. Comput. Appl. 36(1): 167-177 (2013) - [j31]Tao Huang, Evangeline F. Y. Young:
ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 882-893 (2013) - [j30]Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Evangeline F. Y. Young:
Ripple: A Robust and Effective Routability-Driven Placer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1546-1556 (2013) - [c57]Jian Kuang, Evangeline F. Y. Young:
An efficient layout decomposition approach for triple patterning lithography. DAC 2013: 69:1-69:6 - [c56]Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young:
Ripple 2.0: high quality routability-driven placement via global router integration. DAC 2013: 152:1-152:6 - [c55]Xu He, Wing-Kai Chow, Evangeline F. Y. Young:
SRP: simultaneous routing and placement for congestion refinement. ISPD 2013: 108-113 - 2012
- [j29]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 255-259 (2012) - [j28]Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young:
Postplacement Voltage Island Generation. ACM Trans. Design Autom. Electr. Syst. 17(1): 4:1-4:15 (2012) - [c54]Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young:
Crosslink insertion for variation-driven clock network construction. ACM Great Lakes Symposium on VLSI 2012: 321-326 - [c53]Tao Huang, Evangeline F. Y. Young:
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles. ICCAD 2012: 144-151 - 2011
- [j27]Qiang Ma, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young:
Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 85-95 (2011) - [j26]Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 167-179 (2011) - [j25]Tao Huang, Liang Li, Evangeline F. Y. Young:
On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 718-731 (2011) - [j24]Zigang Xiao, Evangeline F. Y. Young:
Placement and Routing for Cross-Referencing Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1000-1010 (2011) - [j23]Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou:
MSV-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1152-1162 (2011) - [c52]Qiang Ma, Hui Kong, Martin D. F. Wong
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. ASP-DAC 2011: 843-848 - [c51]Tao Huang, Evangeline F. Y. Young:
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles. DAC 2011: 164-169 - [c50]Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong
An optimal algorithm for layer assignment of bus escape routing on PCBs. DAC 2011: 176-181 - [c49]Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong
A monte-carlo floating-point unit for self-validating arithmetic. FPGA 2011: 199-208 - [c48]Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young:
Ripple: An effective routability-driven placer by iterative cell movement. ICCAD 2011: 74-79 - [c47]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Grid-to-ports clock routing for high performance microprocessor designs. ISPD 2011: 21-28 - 2010
- [j22]Qiang Ma, Evangeline F. Y. Young:
Multivoltage Floorplan Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 607-617 (2010) - [j21]Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng:
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. 15(4): 33:1-33:22 (2010) - [c46]Zigang Xiao, Evangeline F. Y. Young:
CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. ASP-DAC 2010: 269-274 - [c45]Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
A dual-MST approach for clock network synthesis. ASP-DAC 2010: 467-473 - [c44]Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young:
Fixed-outline thermal-aware 3D floorplanning. ASP-DAC 2010: 561-567 - [c43]Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young:
Local clock skew minimization using blockage-aware mixed tree-mesh clock network. ICCAD 2010: 458-462 - [c42]Tao Huang, Evangeline F. Y. Young:
Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach. ICCAD 2010: 610-613 - [c41]Linfu Xiao, Evangeline F. Y. Young, Xiao-Yong He, Kong-Pang Pun:
Practical placement and routing techniques for analog circuit designs. ICCAD 2010: 675-679 - [c40]Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96 - [c39]Zigang Xiao, Evangeline F. Y. Young:
Droplet-routing-aware module placement for cross-referencing biochips. ISPD 2010: 193-199
2000 – 2009
- 2009
- [j20]Chiu-Wing Sham
Block flipping and white space distribution for wirelength minimization. Integr. 42(2): 246-253 (2009) - [j19]Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu:
Handling routability in floorplan design with twin binary trees. Integr. 42(4): 449-456 (2009) - [j18]Chiu-Wing Sham
Congestion prediction in early stages of physical design. ACM Trans. Design Autom. Electr. Syst. 14(1): 12:1-12:18 (2009) - [c38]Linfu Xiao, Evangeline F. Y. Young:
Analog placement with common centroid and 1-D symmetry constraints. ASP-DAC 2009: 353-360 - [c37]Liang Li, Zaichen Qian, Evangeline F. Y. Young:
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. ICCAD 2009: 21-25 - [c36]Zaichen Qian, Evangeline F. Y. Young:
Multi-voltage floorplan design with optimal voltage assignment. ISPD 2009: 13-18 - 2008
- [j17]Jill H. Y. Law, Evangeline F. Y. Young:
Multi-bend bus driven floorplanning. Integr. 41(2): 306-316 (2008) - [j16]Chiu-Wing Sham
Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. 13(1): 21:1-21:13 (2008) - [c35]Tilen Ma, Evangeline F. Y. Young:
TCG-based multi-bend bus driven floorplanning. ASP-DAC 2008: 192-197 - [c34]Qiang Ma, Evangeline F. Y. Young:
Network flow-based power optimization under timing constraints in MSV-driven floorplanning. ICCAD 2008: 1-8 - [c33]Liang Li, Evangeline F. Y. Young:
Obstacle-avoiding rectilinear Steiner tree construction. ICCAD 2008: 523-528 - [c32]Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59 - [r3]Evangeline F. Y. Young:
Slicing Floorplan Orientation. Encyclopedia of Algorithms 2008 - [r2]Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang:
Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Evangeline F. Y. Young:
Floorplan Representations. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j15]Qiang Xu
Test scheduling for built-in self-tested embedded SRAMs with data retention faults. IET Comput. Digit. Tech. 1(3): 256-264 (2007) - [j14]Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu:
Wire Retiming Problem With Net Topology Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1648-1660 (2007) - [j13]Chiu-Wing Sham
Area reduction by deadspace utilization on interconnect optimized floorplan. ACM Trans. Design Autom. Electr. Syst. 12(1): 3:1-3:11 (2007) - [c31]Qiang Ma, Evangeline F. Y. Young, Kong-Pang Pun:
Analog placement with common centroid constraints. ICCAD 2007: 579-585 - [c30]Qiang Ma, Evangeline F. Y. Young:
Voltage island-driven floorplanning. ICCAD 2007: 644-649 - 2006
- [c29]Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu:
Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114 - [c28]Qiang Xu
Retention-Aware Test Scheduling for BISTed Embedded SRAMs. ETS 2006: 83-88 - [c27]Royce L. S. Ching, Evangeline F. Y. Young:
Shuttle mask floorplanning with modified alpha-restricted grid. ACM Great Lakes Symposium on VLSI 2006: 85-90 - [c26]Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching:
Block alignment in 3D floorplan using layered TCG. ACM Great Lakes Symposium on VLSI 2006: 376-380 - [c25]Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu:
Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354 - [c24]Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu:
Post-placement voltage island generation. ICCAD 2006: 641-646 - 2005
- [c23]Chiu-Wing Sham
Congestion prediction in floorplanning. ASP-DAC 2005: 1107-1110 - [c22]Jill H. Y. Law, Evangeline F. Y. Young:
Multi-bend bus driven floorplanning. ISPD 2005: 113-120 - [c21]Chiu-Wing Sham
Congestion prediction in early stages. SLIP 2005: 91-98 - 2004
- [j12]Chris C. N. Chu, Evangeline F. Y. Young:
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 71-79 (2004) - [j11]Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
Placement constraints in floorplan design. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 735-745 (2004) - [c20]Dennis K. Y. Tong, Evangeline F. Y. Young:
Performance-driven register insertion in placement. ISPD 2004: 53-60 - 2003
- [j10]Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 457-469 (2003) - [j9]Chiu-Wing Sham
Routability-driven floorplanner with buffer block planning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 470-480 (2003) - [j8]Wing Seung Yuen, Evangeline F. Y. Young:
Slicing floorplan with clustering constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 652-658 (2003) - [j7]Wai-Kei Mak, Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 952-959 (2003) - [c19]Keith W. C. Wong, Evangeline F. Y. Young:
Fast buffer planning and congestion optimization in interconnect-driven floorplanning. ASP-DAC 2003: 411-416 - [c18]Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou:
Interconnect-driven floorplanning by searching alternative packings. ASP-DAC 2003: 417-422 - [c17]Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu:
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861 - [c16]Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak:
Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI 2003: 203-206 - [c15]Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu:
Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226 - 2002
- [c14]Wai-Chiu Wong, Chiu-Wing Sham
Congestion Estimation with Buffer Planning in Floorplan Design. DATE 2002: 696-701 - [c13]Chris C. N. Chu, Evangeline F. Y. Young:
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101 - [c12]Chiu-Wing Sham, Evangeline F. Y. Young:
Routability driven floorplanner with buffer block planning. ISPD 2002: 50-55 - [c11]Wai-Kei Mak, Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD 2002: 190-195 - [c10]Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201 - [c9]Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. ASP-DAC/VLSI Design 2002: 661- - 2001
- [j6]Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong:
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 687-692 (2001) - [j5]Evangeline F. Y. Young, Martin D. F. Wong
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 800-807 (2001) - [c8]Wing Seung Yuen, Fung Yu Young:
Slicing floorplan with clustering constraints. ASP-DAC 2001: 503-508 - 2000
- [j4]Evangeline F. Y. Young, Martin D. F. Wong
Slicing floorplans with range constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 272-278 (2000) - [c7]Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong:
Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179
1990 – 1999
- 1999
- [j3]Fung Yu Young, Chris C. N. Chu, D. F. Wong
Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999) - [j2]Evangeline F. Y. Young, Martin D. F. Wong
Slicing floorplans with boundary constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1385-1389 (1999) - [c6]Fung Yu Young, D. F. Wong
Slicing Floorplans with Boundary Constraint. ASP-DAC 1999: 17-20 - [c5]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong
Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 - [c4]Fung Yu Young, D. F. Wong
Slicing floorplans with range constraint. ISPD 1999: 97-102 - 1998
- [c3]Fung Yu Young, D. F. Wong
Slicing floorplans with pre-placed modules. ICCAD 1998: 252-258 - 1997
- [j1]F. Y. Young, D. F. Wong
How good are slicing floorplans? Integr. 23(1): 61-73 (1997) - [c2]Fung Yu Young, D. F. Wong
On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD 1997: 482-488 - [c1]Fung Yu Young, D. F. Wong
How good are slicing floorplans?. ISPD 1997: 144-149
Coauthor Index
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