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Qin Wang 0009
Person information
- affiliation: Shanghai Jiao Tong University, Department of Micro/Nano Electronics, China
Other persons with the same name
- Qin Wang — disambiguation page
- Qin Wang 0001 — China Jiliang University, Department of Mathematics, Hangzhou, China (and 1 more)
- Qin Wang 0002
— New York Institute of Technology, School of Engineering and Computing Sciences, NY, USA (and 2 more)
- Qin Wang 0003
- Qin Wang 0004
- Qin Wang 0005
- Qin Wang 0006
- Qin Wang 0007 — University of Maryland, College Park, MD, USA
- Qin Wang 0008
- Qin Wang 0010 — University of California, San Francisco, CA, USA
- Qin Wang 0011
- Qin Wang 0012 — Zhejiang Wanli University, Ningbo, China
- Qin Wang 0013
- Qin Wang 0014 — South China University of Technology, Guangzhou, China
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2020 – today
- 2024
- [j25]Kunyue Li
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Syst. Appl. 249: 123828 (2024) - [j24]Zihan Zhang
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 176-188 (2024) - [j23]Chen Yin
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1163-1176 (2024) - [j22]Weidong Yang
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2854-2867 (2024) - [j21]Pengyu Liu
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4640-4652 (2024) - [c37]Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. ASPDAC 2024: 225-230 - [c36]Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. ASPDAC 2024: 460-465 - [c35]Lei Xu
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. DAC 2024: 232:1-232:6 - [c34]Wenhui Zhang
A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System. ACM Great Lakes Symposium on VLSI 2024: 125-131 - [c33]Duo Yu
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. ACM Great Lakes Symposium on VLSI 2024: 357-363 - [c32]Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang:
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. ISCAS 2024: 1-5 - [i1]Ao Liu, Jie Han, Qin Wang, Zhigang Mao, Honglan Jiang:
An Architectural Error Metric for CNN-Oriented Approximate Multipliers. CoRR abs/2408.12836 (2024) - 2023
- [j20]Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu
Exploiting bit sparsity in both activation and weight in neural networks accelerators. Integr. 88: 400-409 (2023) - [j19]Chen Yin
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 874-886 (2023) - [j18]Yanan Sun
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2048-2061 (2023) - [j17]Bingxi Pei
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3787-3791 (2023) - [c31]Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing:
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. ASICON 2023: 1-4 - [c30]Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang:
High-Performance Genomic Analysis Heterogeneous System Using OpenCL. ASICON 2023: 1-4 - [c29]Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang:
An NoC-based CNN Accelerator for Edge Computing. ASICON 2023: 1-4 - [c28]Yuqing Yang, Weidong Yang
An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC 2023: 122-127 - [c27]Pengyu Liu
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. FPL 2023: 116-122 - [c26]Shuya Ji
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. ICCD 2023: 54-61 - [c25]Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang:
RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) 2023: 352-364 - 2022
- [j16]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He:
Hierarchical photoelectric hybrid packet switching network for high-performance computing. JOCN 14(8): 680-690 (2022) - [j15]Guochao Deng
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j14]Zihan Zhang
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2094-2106 (2022) - [j13]Taozhong Li
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Trans. Design Autom. Electr. Syst. 27(6): 57:1-57:22 (2022) - [j12]Shengzhao Li
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1587-1600 (2022) - [c24]Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing:
Boosting ReRAM-based DNN by Row Activation Oversubscription. ASP-DAC 2022: 604-609 - 2021
- [c23]Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing:
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity 2021: 180-185 - [c22]Chen Yin
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE 2021: 1394-1399 - [c21]Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang:
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. ISCAS 2021: 1-5 - [c20]Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing:
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. ISCAS 2021: 1-5 - 2020
- [j11]Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao:
Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. 12(7): 1196 (2020) - [j10]Zhongyuan Zhao
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 31(9): 2201-2219 (2020) - [c19]Hongcheng Mo, Jianfei Jiang, Qin Wang, Dong Yin, Pengyu Dong, Jingjun Tian:
Frequency Attention Network: Blind Noise Removal for Real Images. ACCV (2) 2020: 168-184 - [c18]Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing:
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI 2020: 345-350 - [c17]Tu Hong, Ning Guan, Chen Yin
Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j9]Qin Wang, Fengyi Shen, Linyao Shen, Jia Huang, Weiguang Sheng:
Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network. J. Digit. Imaging 32(6): 971-979 (2019) - [j8]Shuo Zhang
Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 16(6): 864-868 (2019) - [j7]Yanan Sun
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 753-757 (2019) - [j6]Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing:
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. 24(2): 25:1-25:22 (2019) - [j5]Qin Wang, Zechen Liu, Jianfei Jiang
A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 458-467 (2019) - [c16]Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang:
A New Approximate Multiplier Design for Digital Signal Processing. ASICON 2019: 1-4 - [c15]Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing:
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS 2019: 1-5 - 2018
- [j4]Jianfei Wang
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. IEEE Trans. Parallel Distributed Syst. 29(3): 586-599 (2018) - [c14]Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao:
Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE 2018: 1087-1092 - [c13]Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao:
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig 2018: 1-8 - 2017
- [j3]Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao:
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. Integr. 59: 23-30 (2017) - [c12]Xianjie Long, Qin Wang, Jianfei Jiang, Nin Guan:
An on-chip circuit for timing measurement of SRAM IP. ASICON 2017: 569-572 - [c11]Chaoyang Li, Qin Wang, Jianfei Jiang, Nin Guan:
A metastability-based true random number generator on FPGA. ASICON 2017: 738-741 - 2016
- [j2]Jianfei Jiang
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25(10): 1650121:1-1650121:31 (2016) - 2015
- [j1]Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao:
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12(8): 20150111 (2015) - [c10]Sai Hu, Qin Wang, Zheng Guo, Jing Xie, Zhigang Mao:
Fault detection and redundancy design for TSVs in 3D ICs. ASICON 2015: 1-4 - [c9]Jiayi Hu, Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao:
A crosstalk avoidance scheme based on re-layout of signal TSV. ASICON 2015: 1-4 - [c8]Jiachao Chen, Qin Wang, Zheng Guo, Junrong Liu, Haihua Gu:
A Circuit Design of SMS4 against Chosen Plaintext Attack. CIS 2015: 371-374 - [c7]Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao:
A contactless testing methodology for pre-bond interposer. MWSCAS 2015: 1-4 - 2013
- [c6]Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao:
TSVs-aware floorplanning for 3D integrated circuit. ASICON 2013: 1-4 - [c5]Zhenyang Chen, Qin Wang, Jing Xie, Jin Tian, Jianfei Jiang, Yufei Li, Wen Yin:
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. ISCAS 2013: 2646-2649 - 2012
- [c4]Shunqing Yan, Yongxin Zhu, Qiannan Zhang, Qin Wang, Ming Ni, Guangwei Xie:
A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain. ICDCS Workshops 2012: 330-335 - [c3]Shunqing Yan, Liang Hong, Weifeng He, Qin Wang:
Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC. SITIS 2012: 225-229 - 2011
- [c2]Can Wang, Qin Wang, Jianfei Jiang:
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code. ASICON 2011: 629-632 - [c1]Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao:
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. ISCAS 2011: 1487-1490
Coauthor Index
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last updated on 2024-12-26 01:55 CET by the dblp team
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