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Jens Sparsø
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2020 – today
- 2024
- [j20]Zuzana Jelcicová
, Evangelia Kasapaki, Oskar Andersson
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 150-163 (2024) - [c62]Alessandro Cerioli, Riccardo Miccini, Clément Laroche, Tobias Piechowiak, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl:
NeuralCasting: A Front-End Compilation Infrastructure for Neural Networks. IOTSMS 2024: 161-168 - [i2]Riccardo Miccini
Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms. CoRR abs/2402.12263 (2024) - 2023
- [c61]Kasper Hesse
Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements. DSD 2023: 168-175 - [c60]Zuzana Jelcicová
A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. ISCAS 2023: 1-5 - [c59]Riccardo Miccini
Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting. MLSP 2023: 1-6 - [i1]Riccardo Miccini, Alaa Zniber, Clément Laroche, Tobias Piechowiak, Martin Schoeberl, Luca Pezzarossa, Ouassim Karrakchou, Jens Sparsø, Mounir Ghogho:
Dynamic nsNet2: Efficient Deep Noise Suppression with Early Exiting. CoRR abs/2308.16678 (2023) - 2022
- [j19]Jens Sparsø
Comparing timed-division multiplexing and best-effort networks-on-chip. J. Syst. Archit. 133: 102766 (2022) - 2021
- [c58]Eleftherios Kyriakakis, Jens Sparsø
Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller. ETFA 2021: 1-8 - [c57]Zuzana Jelcicová
PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks. EUSIPCO 2021: 416-420 - [c56]Eleftherios Kyriakakis, Jens Sparsø
Synchronizing Real-Time Tasks in Time-Triggered Networks. ISORC 2021: 11-19 - 2020
- [j18]Eleftherios Kyriakakis, Maja Lund, Luca Pezzarossa, Jens Sparsø
A time-predictable open-source TTEthernet end-system. J. Syst. Archit. 108: 101744 (2020) - [c55]Zuzana Jelcicová
A Neural Network Engine for Resource Constrained Embedded Systems. ACSSC 2020: 125-131 - [c54]Eleftherios Kyriakakis, Jens Sparsø
Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress. EMSOFT 2020: 15-17
2010 – 2019
- 2019
- [j17]Tórur Biskopstø Strøm, Jens Sparsø
Hardlock: Real-time multicore locking. J. Syst. Archit. 97: 467-476 (2019) - [c53]Martin Schoeberl
A Minimal Network Interface for a Simple Network-on-Chip. ARCS 2019: 295-307 - [c52]Adrian Mardari, Zuzana Jelcicová
Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking. ASYNC 2019: 9-18 - [c51]Martin Schoeberl
Scratchpad Memories with Ownership. DATE 2019: 1216-1221 - [c50]Eleftherios Kyriakakis, Jens Sparsø
Implementing time-triggered communication over a standard ethernet switch. IoT-Fog@IoTDI 2019: 21-25 - [c49]Oktay Baris, Shibarchi Majumder, Tórur Biskopstø Strøm, Anders la Cour-Harbo
Demonstration of a Time-predictable Flight Controller on a Multicore Processor. ISORC 2019: 95-96 - [c48]Maja Lund, Luca Pezzarossa, Jens Sparsø
A Time-predictable TTEthenet Node. ISORC 2019: 229-233 - [c47]Martin Schoeberl
S4NOC: a minimalistic network-on-chip for real-time multicores. NoCArc@MICRO 2019: 8:1-8:6 - 2018
- [j16]Martin Schoeberl
A Multicore Processor for Time-Critical Applications. IEEE Des. Test 35(2): 38-47 (2018) - [j15]Jens Sparsø
Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016. Microprocess. Microsystems 60: 38-39 (2018) - [j14]Luca Pezzarossa, Andreas Toftegaard Kristensen
Using dynamic partial reconfiguration of FPGAs in real-Time systems. Microprocess. Microsystems 61: 198-206 (2018) - [c46]Eleftherios Kyriakakis, Jens Sparsø
Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol. RTNS 2018: 51-60 - 2017
- [j13]Rasmus Bo Sørensen, Luca Pezzarossa, Martin Schoeberl
A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip. J. Syst. Archit. 74: 1-13 (2017) - [c45]Luca Pezzarossa, Martin Schoeberl
A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. ISORC 2017: 92-100 - [c44]Martin Schoeberl
Timing Organization of a Real-Time Multicore Processor. NGCAS 2017: 89-92 - [c43]Andreas Toftegaard Kristensen
High-level synthesis for reduction of WCET in real-time systems. NORCAS 2017: 1-6 - [c42]Luca Pezzarossa, Andreas Toftegaard Kristensen
Can real-time systems benefit from dynamic partial reconfiguration? NORCAS 2017: 1-6 - 2016
- [j12]Evangelia Kasapaki, Martin Schoeberl
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 479-492 (2016) - [c41]Rasmus Bo Sørensen, Luca Pezzarossa, Jens Sparsø
An area-efficient TDM NoC supporting reconfiguration for mode changes. NOCS 2016: 1-4 - [c40]André Rocha, Cláudio Silva, Rasmus Bo Sørensen, Jens Sparsø
Avionics Applications on a Time-Predictable Chip-Multiprocessor. PDP 2016: 777-785 - [c39]Luca Pezzarossa, Martin Schoeberl
Reconfiguration in FPGA-based multi-core platforms for hard real-time applications. ReCoSoC 2016: 1-8 - [c38]Rasmus Bo Sørensen, Martin Schoeberl
State-based Communication on Time-predictable Multicore Processors. RTNS 2016: 225-234 - 2015
- [j11]Martin Schoeberl
T-CREST: Time-predictable multi-core architecture for embedded systems. J. Syst. Archit. 61(9): 449-471 (2015) - [c37]Evangelia Kasapaki, Jens Sparsø
The Argo NOC: Combining TDM and GALS. ECCTD 2015: 1-4 - [c36]Martin Schoeberl, Rasmus Bo Sørensen, Jens Sparsø:
Models of Communication for Multicore Processors. ISORC Workshops 2015: 9-16 - [c35]Rasmus Bo Sørensen, Wolfgang Puffitsch
Message Passing on a Time-predictable Multicore Processor. ISORC 2015: 51-59 - [c34]Luca Pezzarossa, Rasmus Bo Sørensen, Martin Schoeberl
Interfacing hardware accelerators to a time-division multiplexing network-on-chip. NORCAS 2015: 1-4 - 2014
- [c33]Evangelia Kasapaki, Jens Sparsø
Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers. ASYNC 2014: 45-52 - [c32]Rasmus Bo Sørensen, Jens Sparsø
A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip. ISORC 2014: 309-316 - [c31]I. Kotleas, D. Humphreys, Rasmus Bo Sørensen, Evangelia Kasapaki, Florian Brandner, Jens Sparsø
A loosely synchronizing asynchronous router for TDM-scheduled NOCs. NOCS 2014: 151-158 - [c30]Mathias Herlev, Christian Keis Poulsen, Jens Sparsø
Open core protocol (OCP) clock domain crossing interfaces. NORCHIP 2014: 1-6 - [c29]Christoph Thomas Muller, Evangelia Kasapaki, Rasmus Bo Sørensen, Jens Sparsø
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools. NORCHIP 2014: 1-6 - [c28]Martin Schoeberl
A Time-Predictable Memory Network-on-Chip. WCET 2014: 53-62 - 2013
- [c27]Jens Sparsø
An area-efficient network interface for a TDM-based network-on-chip. DATE 2013: 1044-1047 - [c26]Evangelia Kasapaki, Jens Sparsø
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip. DSD 2013: 319-326 - [c25]Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. VLSI-SoC 2013: 380-385 - 2012
- [c24]Jens Sparsø
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip. ACSD 2012: 1-5 - [c23]Martin Schoeberl
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems. NOCS 2012: 152-160 - [c22]Rasmus Bo Sørensen, Martin Schoeberl
A light-weight statically scheduled network-on-chip. NORCHIP 2012: 1-6 - [e1]Jens Sparsø, Montek Singh, Pascal Vivet:
18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1360-5 [contents] - 2011
- [j10]Omer Can Akgun
Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection. IET Comput. Digit. Tech. 5(4): 342-353 (2011) - [j9]Matthias Bo Stuart
Analytical derivation of traffic patterns in cache-coherent shared-memory systems. Microprocess. Microsystems 35(7): 632-642 (2011) - [j8]Matthias Bo Stuart
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation. ACM Trans. Embed. Comput. Syst. 10(4): 45:1-45:26 (2011) - 2010
- [c21]Omer Can Akgun
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study. ASYNC 2010: 41-51
2000 – 2009
- 2009
- [j7]Sune Fallgaard Nielsen, Jens Sparsø
Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 248-261 (2009) - [c20]Sune Fallgaard Nielsen, Jens Sparsø
A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow. ASYNC 2009: 185-194 - [c19]Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø:
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. CODES+ISSS 2009: 481-490 - [c18]Jens Sparsø
Current trends in high-level synthesis of asynchronous circuits. ICECS 2009: 347-350 - 2008
- [j6]Shankar Mahadevan, Federico Angiolini, Jens Sparsø
A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 109-122 (2008) - [c17]Mikkel Bystrup Stensgaard, Jens Sparsø:
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. NOCS 2008: 55-64 - 2007
- [c16]Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. DATE 2007: 648-653 - 2006
- [c15]Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. DSD 2006: 641-648 - [c14]Tobias Bjerregaard, Jens Sparsø
Packetizing OCP Transactions in the MANGO Network-on-Chip. DSD 2006: 657-664 - 2005
- [c13]Tobias Bjerregaard, Jens Sparsø
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. ASYNC 2005: 34-43 - [c12]Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø
A Network Traffic Generator Model for Fast Network-on-Chip Simulation. DATE 2005: 780-785 - [c11]Tobias Bjerregaard, Jens Sparsø
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. DATE 2005: 1226-1231 - [c10]Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. SoC 2005: 171-174 - [c9]Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini
A Traffic Injection Methodology with Support for System-Level Synchronization. VLSI-SoC 2005: 145-161 - 2004
- [j5]Özgün Paker, Jens Sparsø
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. J. VLSI Signal Process. 37(1): 95-110 (2004) - [c8]Sune Fallgaard Nielsen, Jens Sparsø
Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. DSD 2004: 298-305 - [c7]Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø:
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. PATMOS 2004: 301-310 - 2002
- [c6]Vojin G. Oklobdzija, Jens Sparsø:
Future directions in clocking multi-ghz systems. ISLPED 2002: 219
1990 – 1999
- 1999
- [j4]Lars Skovby Nielsen, Jens Sparsø:
Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid. Proc. IEEE 87(2): 268-281 (1999) - 1998
- [c5]Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. ASYNC 1998: 108- - 1996
- [c4]Lars Skovby Nielsen, Jens Sparsø
A low-power asynchronous data-path for a FIR filter bank. ASYNC 1996: 197-207 - 1994
- [j3]Lars Skovby Nielsen, Cees Niessen, Jens Sparsø
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 391-397 (1994) - 1993
- [j2]Jens Sparsø
Delay-insensitive multi-ring structures. Integr. 15(3): 313-340 (1993) - [c3]Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup:
Design of Self-timed Multipliers: A Comparison. Asynchronous Design Methodologies 1993: 165-179 - 1992
- [c2]Jens Sparsø
Design of delay insensitive circuits using multi-ring structures. EURO-DAC 1992: 15-20 - 1991
- [j1]Erik Paaske, Steen Pedersen, Jens Sparsø
An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders. Integr. 12(1): 79-91 (1991) - [c1]Jens Sparsø, Steen Pedersen, Erik Paaske:
Design of a Fully Parallel Viterbi Decoder. VLSI 1991: 29-38
Coauthor Index
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