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IEEE Transactions on Very Large Scale Integration Systems, Volume 24
Volume 24, Number 1, January 2016
- Nishit Ashok Kapadia, Sudeep Pasricha:
A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs. 3-16 - Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang:
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. 17-25 - Mohammadreza Ashraf, Nasser Masoumi:
A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers. 26-37 - Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen:
Test Pattern Modification for Average IR-Drop Reduction. 38-49 - Tay-Jyi Lin, Ting-Yu Shyu:
Speculative Lookahead for Energy-Efficient Microprocessors. 50-57 - Brian P. Degnan
, Bo Marr, Jennifer Hasler:
Assessing Trends in Performance per Watt for Signal Processing Applications. 58-66 - Jian Wang
A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT. 67-78 - Qi Guo, Xi Li, Chao Wang, Xuehai Zhou:
Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC. 79-91 - Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. 92-102 - Sparsh Mittal
EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches. 103-114 - Chao Sun
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. 115-128 - Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman:
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing. 129-138 - Kejie Huang
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array. 139-150 - Hamad Marzouqi, Mahmoud Al-Qutayri
A High-Speed FPGA Implementation of an RSD-Based ECC Processor. 151-164 - Mohamed S. Abdelfattah
Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses. 165-177 - Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk:
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. 178-191 - Shaodi Wang, Andrew Pan
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices. 192-205 - Ioannis Vourkas
Alternative Architectures Toward Reliable Memristive Crossbar Memories. 206-217 - Mohit Kumar Gupta, Mohd. Hasan
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits. 218-222 - Meysam Asghari, Mohammad Yavari
Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors. 223-232 - Neelanjana Pal, Prajit Nandi, Riju Biswas, Ashvinkumar G. Katakwar:
Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC. 233-242 - Yang Xu, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, Zhihua Wang:
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration. 243-255 - Maryam Zare, Mohammad Maymandi-Nejad
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply. 256-265 - Wei Jhih Wang, Chang Hong Lin:
Code Compression for Embedded Systems Using Separated Dictionaries. 266-275 - Jedrzej Kufel, Peter R. Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough:
Sequence-Aware Watermark Design for Soft IP Embedded Processors. 276-289 - Chuang Bai, Xuecheng Zou, Kui Dai:
A Novel Thyristor-Based Silicon Physical Unclonable Function. 290-300 - Benjamin Carrión Schäfer
Source Code Error Detection in High-Level Synthesis Functional Verification. 301-312 - Kamran Rahmani, Sudhi Proch, Prabhat Mishra
Efficient Selection of Trace and Scan Signals for Post-Silicon Debug. 313-323 - Benjamin Carrión Schäfer
Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control. 324-328 - Debajit Bhattacharya, Niraj K. Jha:
TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. 329-333 - Liang Shi, Yejia Di, Mengying Zhao, Chun Jason Xue
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems. 334-337 - Qingqing Yang, Xiaofang Zhou, Gerald E. Sobelman, Xinxin Li:
Network-on-Chip for Turbo Decoders. 338-342 - Michael Moeng, Haifeng Xu, Rami G. Melhem, Alex K. Jones
ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access. 343-347 - Oscal T.-C. Chen, Cheng-Ta Chan, Robin R.-B. Sheen:
Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers. 348-352 - Jens Müller, Jan Müller, Robert Braunschweig, Ronald Tetzlaff
A Cellular Network Architecture With Polynomial Weight Functions. 353-357 - Robert Giterman
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. 358-362 - Chan-Hui Jeong, Ammar Abdullah
All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications. 363-367 - Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, Kiamal Z. Pekmestzi:
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. 368-372 - C. B. Kushwah, Santosh Kumar Vishvakarma
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. 373-377 - Jesús Moreno, Michel Renovell, Víctor H. Champac:
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. 378-382 - Vianney Lapotre
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. 383-387 - Jaeyong Chung
Defect Diagnosis via Segment Delay Learning. 388-392 - Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers. 393-397 - Tooraj Nikoubin, Mahdieh Grailoo
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology. 398-402 - Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila
Polymorphic Configuration Architecture for CGRAs. 403-407 - Ching-Che Chung
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. 408-412
Volume 24, Number 2, February 2016
- Sumedh Dhabu, Vinod Achutavarrier Prasad
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics. 413-420 - Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels. 421-433 - Shiann-Rong Kuang, Kun-Yi Wu, Ren-Yao Lu:
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. 434-443 - Basant Kumar Mohanty
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. 444-452 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. 453-464 - Masoud Oveis Gharan, Gul N. Khan
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems. 465-478 - Evangelia Kasapaki, Martin Schoeberl
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. 479-492 - Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. 493-506 - Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. 507-520 - Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell. 521-529 - Juan Antonio Clemente
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems. 530-543 - Tao Feng, Nizar Lajnef, Shantanu Chakrabartty:
Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry. 544-554 - Wei Wang, James F. Buckwalter:
Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication. 555-566 - Daniel Günther, Rainer Leupers, Gerd Ascheid:
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing. 567-577 - Shuai Chen, Hao Li, Patrick Yin Chiang:
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects. 578-586 - Chung-An Shen, Chia-Po Yu, Chien-Hao Huang:
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes. 587-599 - Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. 600-612 - Jinhui Wang, Na Gong, Eby G. Friedman:
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors. 613-624 - Shu-Yung Bin, Shih-Feng Lin, Ya Ching Cheng, Wen-Rong Liau, Alex Hou, Mango C.-T. Chao:
Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics. 625-637 - Mousumi Bhanja
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application. 638-649 - Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Nasser Masoumi, Deming Chen:
Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis. 650-663 - Qiang Liu, Ming Gao, Qijun Zhang:
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development. 664-677 - Sadia Alam, S. M. Rezaul Hasan
A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription. 678-691 - Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. 692-705 - Chen Hou
A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes. 706-719 - Jun-Ping Wang, Run-Sen Xing, Dan Xu, Yong-Bang Su, Rui-Ping Feng, Rong Wei, Ya-Ning Li, Teng-Wei Zhao:
Redundant Via Insertion Based on SCA. 720-728 - Mehmet Avci, Farid N. Najm:
Verification of the Power and Ground Grids Under General and Hierarchical Constraints. 729-742 - Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi:
Design for Testability of Sleep Convention Logic. 743-753 - Jihyuck Jo
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. 754-758 - Yung-Hsiang Ho, Chia-Yu Yao:
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register. 759-763 - Jinyoung Kim, Sang-Hoon Park, Hyeokjun Seo, Ki-Whan Song, Sungroh Yoon, Eui-Young Chung:
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices. 764-768 - Zhen Gao, Pedro Reviriego
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks. 769-773 - Alexander E. Shapiro, Eby G. Friedman:
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits. 774-778 - Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang:
Efficient Synchronization for Distributed Embedded Multiprocessors. 779-783 - Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi:
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. 784-788 - Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim:
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. 789-793 - Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, Seung-Tak Ryu:
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. 794-798 - Victor Dumitriu, Lev Kirischian:
SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations. 799-802 - Amirreza Alizadeh
Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects. 803-807 - M. Hassan Najafi
A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing. 808-812
Volume 24, Number 3, March 2016
- Pranav S. Vaidya, John Jaehwan Lee
Symbiote Coprocessor Unit - A Streaming Coprocessor for Data Stream Acceleration. 813-826 - Moein Kianpour
A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM. 827-836 - Osama Ullah Khan, David D. Wentzloff:
Hardware Accelerator for Probabilistic Inference in 65-nm CMOS. 837-845 - Arnab Raha
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding. 846-857 - Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. 858-870 - Jongmin Lee, Soontae Kim:
Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems. 871-883 - Mahmoud Zangeneh, Ajay Joshi:
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization. 884-896 - Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. 897-908 - Rabab Ezz-Eldin, Magdy A. El-Moursy
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design. 909-919 - Jintao Zheng, Ning Wu, Lei Zhou, Yunfei Ye, Ke Sun:
DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures. 920-931 - Mojtaba Ebrahimi, Parthasarathy Murali B. Rao, Razi Seyyedi, Mehdi Baradaran Tahoori:
Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames. 932-943 - Seyedhamidreza Motaman, Swaroop Ghosh:
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches. 944-953 - Mohammad Reza Jokar, Mohammad Arjomand, Hamid Sarbazi-Azad:
Sequoia: A High-Endurance NVM-Based Cache Architecture. 954-967 - Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra:
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. 968-978 - Jianxiao Yang, Benoit Geller
An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel. 979-991 - Xuanyao Fong
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. 992-1002 - Yasmin Halawani, Baker Mohammad
Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications. 1003-1014 - Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. 1015-1024 - Won Namgoong:
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop. 1025-1035 - Henda Aridhi, Mohamed H. Zaki
Enhancing Model Order Reduction for Nonlinear Analog Circuit Simulation. 1036-1049 - Ishita Mukhopadhyay, Mustansir Yunus Mukadam, Rajendran Narayanan, Frank O'Mahony, Alyssa B. Apsel:
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O. 1050-1058 - Yu Zheng, Fengchao Zhang, Swarup Bhunia
DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain. 1059-1070 - Seyed Amir Reza Ahmadi Mehr
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division. 1071-1082 - Supeng Liu, Yuanjin Zheng:
A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS. 1083-1091 - Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. 1092-1103 - Yu Xia, Kaiming Nie, Jiangtao Xu, Suying Yao:
A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method. 1104-1117 - Jebreel M. Salem
Dual Use of Power Lines for Design-for-Testability - A CMOS Receiver Design. 1118-1125 - Aoxiang Tang, Niraj K. Jha:
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis. 1126-1139 - Kai He, Sheldon X.-D. Tan, Hai Wang, Guoyong Shi:
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis. 1140-1150 - Eric J. Wyers, Matthew A. Morton, T. C. L. Gerhard Sollner, C. T. Kelley
A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs. 1151-1164 - Hamed Dorosti
Ultralow-Energy Variation-Aware Design: Adder Architecture Study. 1165-1168 - Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. 1169-1173 - Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. 1174-1178 - Doohwang Chang, Jennifer N. Kitchen, Bertan Bakkaloglu
Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits. 1179-1183 - Chan-Keun Kwon, Hoon Ki Kim, Jongsun Park
A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator. 1184-1188 - Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. 1189-1192 - Jiliang Zhang:
A Practical Logic Obfuscation Technique for Hardware Security. 1193-1197 - Shraddha Bodhe, M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
Diagnostic Fail Data Minimization Using an N-Cover Algorithm. 1198-1202 - Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins:
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. 1203-1207 - Amir Kaivani, Seok-Bum Ko
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation. 1208-1211 - Kai He, Sheldon X.-D. Tan:
Corrections to "GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis". 1212
Volume 24, Number 4, April 2016
- Srivatsan Chellappa, Lawrence T. Clark:
SRAM-Based Unique Chip Identifier Techniques. 1213-1222 - Lijuan Li
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m). 1223-1232 - Ujjwal Guin
Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling. 1233-1246 - Lauri Koskinen, Markus Hiienkari, Jani Mäkipää, Matthew J. Turnquist:
Implementing Minimum-Energy-Point Systems With Adaptive Logic. 1247-1256 - Pramod Kumar Meher:
On Efficient Retiming of Fixed-Point Circuits. 1257-1265 - Yuxin Bai
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS. 1266-1279 - S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson:
Hybrid LUT/Multiplexer FPGA Logic Architectures. 1280-1292 - Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang:
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. 1293-1304 - Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. 1305-1318 - Jian Kuang
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. 1319-1332 - Yong Ye, Yong Kang, Chao Zhang, Yipeng Chan, Hanming Wu, Shiuhwuu Lee, Zhitang Song, Bomy Chen:
A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell. 1333-1341 - Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. 1342-1350 - Jaeyoung Park, Tianhao Zheng, Mattan Erez
Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. 1351-1360 - Taehui Na
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM. 1361-1370 - Shivam Verma
Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform. 1371-1376 - Jean-François Pons
RF Power Gating: A Low-Power Technique for Adaptive Radios. 1377-1390 - Jienan Chen, Jianhao Hu, Jiangyun Zhou:
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers. 1391-1401 - Yang Zhao
An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS. 1402-1411 - Thinh Hung Pham
Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization. 1412-1420 - Xiao Liang Tan, Pak Kwong Chan:
A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation. 1421-1429 - Dong Wang
A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS. 1430-1440 - Kuan-Ting Lin, Yu-Wei Cheng, Kea-Tiong Tang:
A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme. 1441-1449 - Taeho Lee, Yong-Hun Kim, Jaehyeong Sim
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. 1450-1459 - Mohammad Hossein Taghavi, Peyman Ahmadi, Leonid Belostotski
A Stagger-Tuned Transimpedance Amplifier. 1460-1469 - Liang-Jen Chen, Shen-Iuan Liu:
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS. 1470-1483 - Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung:
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. 1484-1492 - Ramachandran Venkatasubramanian, Kent Oertle, Sule Ozev:
A Comparator-Based Rail Clamp. 1493-1502 - Daniel Arumí
Prebond Testing of Weak Defects in TSVs. 1503-1514 - Caleb Serafy, Avram Bar-Cohen, Ankur Srivastava
Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling. 1515-1523 - Xiaoyu Xu
3-D IC Interconnect Capacitance Extraction Using Dual Discrete Geometric Methods With Prism Elements. 1524-1534 - Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. 1535-1545 - Weichen Liu
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip. 1546-1559 - Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak:
IP Protection of Mesh NoCs Using Square Spiral Routing. 1560-1573 - Zhehui Wang
Improve Chip Pin Performance Using Optical Interconnects. 1574-1587 - Supriya Aggarwal
Concept, Design, and Implementation of Reconfigurable CORDIC. 1588-1592 - Hooman Farkhani, Ali Peiravi, Farshad Moradi
Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique. 1593-1597 - Hoi Lee:
An Auto-Reconfigurable 2×4× AC-DC Regulator for Wirelessly Powered Biomedical Implants With 28% Link Efficiency Enhancement. 1598-1602 - Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. 1603-1606 - Jian Wang, Zhonghai Lu
A New CDMA Encoding/Decoding Method for on-Chip Communication Network. 1607-1611 - Thian Fatt Tay, Chip-Hong Chang
Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". 1612
Volume 24, Number 5, May 2016
- Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. 1613-1625 - Duckhwan Kim, Saibal Mukhopadhyay:
Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation. 1626-1635 - Taigon Song, Chang Liu, Yarui Peng
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. 1636-1648 - Xianmin Chen, Niraj K. Jha:
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation. 1649-1662 - Viveka Konandur Rajanna
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs. 1663-1674 - Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang:
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. 1675-1687 - Yang Lin, Mark Zwolinski
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors. 1688-1701 - Mehdi Sadi, Mark M. Tehranipoor:
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs. 1702-1714 - Xiaoxiao Wang, Dongrong Zhang, Donglin Su, LeRoy Winemberg, Mark M. Tehranipoor:
A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits. 1715-1727 - Hsuan-Yu Chang, Ching-Yuan Yang
A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs. 1728-1738 - Daniel Arumí
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. 1739-1748 - Debao Wei, Libao Deng, Liyan Qiao, Peng Zhang, Xiyuan Peng:
PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash. 1749-1760 - Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen:
A Leakage Compensation Design for Low Supply Voltage SRAM. 1761-1769 - Yebin Lee
CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System. 1770-1782 - Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Self-Timed Read and Write Operations in STT-MRAM. 1783-1793 - Sandeep Chandran
Area-Aware Cache Update Trackers for Postsilicon Validation. 1794-1807 - Ming-Chang Yang, Yuan-Hao Chang
Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way. 1808-1820 - Ehsan Nasiri, Javeed Shaikh, André Hahn Pereira, Vaughn Betz:
Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs. 1821-1834 - Chun-Po Huang
A Systematic Design Methodology of Asynchronous SAR ADCs. 1835-1848 - Zeinab Torabi
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range. 1849-1857 - Greg Leung, Shaodi Wang, Andrew Pan
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits. 1858-1870 - Chih-Hung Chou, Ta-Wen Kuan, Shovan Barma
A New Binary-Halved Clustering Method and ERT Processor for ASSR System. 1871-1884 - Kejie Huang
Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs. 1885-1894 - Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. 1895-1908 - Payam Masoumi Farahabadi
A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS. 1909-1916 - Fanyi Meng
A 57-to-64-GHz 0.094-mm2 5-bit Passive Phase Shifter in 65-nm CMOS. 1917-1925 - Basant K. Mohanty
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. 1926-1935 - Pascal A. Hager, Andrea Bartolini
Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second. 1936-1949 - Jesus Omar Lacruz
High-Performance NB-LDPC Decoder With Reduction of Message Exchange. 1950-1961 - Nourhan Bayasi, Temesghen Tekeste, Hani H. Saleh
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia. 1962-1974 - Immanuel Raja
A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS. 1975-1983 - Yung-Hsiang Ho, Chia-Yu Yao:
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation. 1984-1992 - Chung-Hsien Chang, Shi-Huang Chen, Bo-Wei Chen, Wen Ji, K. Bharanitharan, Jhing-Fa Wang:
Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing. 1993-1997 - Shouyi Yin, Pengcheng Zhou, Leibo Liu
Trigger-Centric Loop Mapping on CGRAs. 1998-2002 - Amit Chhabra, Yagnesh Dineshbhai Vaderiya:
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM. 2003-2007 - Abhishek Ambede
Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order. 2008-2012
Volume 24, Number 6, June 2016
- Hong-Son Vu
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones. 2013-2025 - Tejinder Singh Sandhu, Kamal El-Sankary:
A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs. 2026-2039 - Mohammad Gholami
Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources. 2040-2049 - Omar Abdelfattah, George Gal, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs. 2050-2061 - Qiang Liu, Qijun Zhang:
Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems. 2062-2074 - Yingnan Cui, Wei Zhang, Vivek Chaturvedi
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems. 2075-2088 - Muhammad Usman Karim Khan, Muhammad Shafique
Power-Efficient Workload Balancing for Video Applications. 2089-2102 - Inkwon Hwang
A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server. 2103-2116 - Ashis Maity
A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications. 2117-2127 - Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Approximate SRAMs With Dynamic Energy-Quality Management. 2128-2141 - Sandeep Mishra
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control. 2142-2151 - Jeongkyu Hong
Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches. 2152-2164 - Bo Wang
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs. 2165-2173 - Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang:
Optimized Built-In Self-Repair for Multiple Memories. 2174-2183 - Fahad Ahmed, Linda S. Milor
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs. 2184-2194 - Zhong Guan, Malgorzata Marek-Sadowska:
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. 2195-2207 - Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi:
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. 2208-2219 - Yao Chen
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. 2220-2233 - Woo-Rham Bae
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. 2234-2243 - Sihwan Kim, Jennifer Hasler, Suma George:
Integrated Floating-Gate Programming Environment for System-Level ICs. 2244-2252 - Suma George, Sihwan Kim, Sahil Shah, Jennifer Hasler, Michelle Collins, Farhan Adil, Richard B. Wunderlich, Stephen Nease, Shubha Ramakrishnan:
A Programmable and Configurable Mixed-Mode FPAA SoC. 2253-2261 - Peng Wang, John McAllister:
Streaming Elements for FPGA Signal and Image Processing Accelerators. 2262-2274 - Marzieh Mollaalipour
Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications. 2275-2285 - Jae Woong Jeong, Afsaneh Nassery, Jennifer N. Kitchen, Sule Ozev:
Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers. 2286-2298 - Moon Seok Kim, Xueqing Li, Huichu Liu, John Sampson, Suman Datta
Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs. 2299-2309 - Joon-Yeong Lee, Jaehyeok Yang, Jong-Hyeok Yoon, Soon-Won Kwon
A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS. 2310-2320 - Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. 2321-2334 - Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures. 2335-2344 - Palkesh Jain
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects. 2345-2358 - Ramprasath S
A Skew-Normal Canonical Model for Statistical Static Timing Analysis. 2359-2368 - Javier Hormigo
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. 2369-2377 - Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A High Throughput List Decoder Architecture for Polar Codes. 2378-2391 - Irith Pomeranz:
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes. 2392-2396 - Hoyoung Tang, Jongsun Park
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors. 2397-2401 - Antony Xavier Glittas
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. 2402-2406 - Fang-Ting Chou, Chung-Chih Hung:
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC. 2407-2411 - Hong-Son Vu, Kuan-Hung Chen:
Corrections to "A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones". 2412
Volume 24, Number 7, July 2016
- Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu:
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. 2413-2425 - Mohammad Salehi, Mohammad Khavari Tavana
Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems. 2426-2437 - Andres F. Gomez, Víctor H. Champac:
Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. 2438-2448 - Xue Liu, Ze-ke Wang, Qing-xu Deng:
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application. 2449-2461 - Zhehui Wang
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. 2462-2474 - Luan H. K. Duong
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. 2475-2487 - Ryan Gary Kim
Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty. 2488-2501 - Tao Zhang, Ping Gui, Sudipto Chakraborty, Tianwei Liu, Guoying Wu
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS. 2502-2510 - Guoying Wu
A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator. 2511-2520 - Woongrae Kim, Chang-Chih Chen, Dae Hyun Kim
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array. 2521-2534 - Sheng-Wei Cheng, Yuan-Hao Chang
Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory. 2535-2547 - Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu
CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. 2548-2561 - Yunjae Suh, Seungnam Choi, Jae-Yoon Sim:
A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC. 2562-2569 - Young-Hwa Kim, SeongHwan Cho:
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. 2570-2579 - Marco Ho
A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages. 2580-2592 - Zhenqi Wei, Peilin Liu, Rongdi Sun, Jun Dai, Zunquan Zhou, Xiangming Geng, Rendong Ying:
HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications. 2593-2597 - Sheng-Lyang Jang, Wei-Chung Cheng, Ching-Wen Hsue:
Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order RLC Resonator. 2598-2602 - Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. 2603-2607 - Sachin Kumar, Chip-Hong Chang
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n-1, 2n, 2n+1}. 2608-2612
Volume 24, Number 8, August 2016
- Krishnendu Chakrabarty
Editorial First TVLSI Best AE and Reviewer Awards. 2613 - V. Mohammed Zackriya
Precharge-Free, Low-Power Content-Addressable Memory. 2614-2621 - Lior Atias, Adam Teman
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. 2622-2633 - Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell. 2634-2642 - Jesus Omar Lacruz
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. 2643-2653 - Hongbin Sun
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device. 2654-2664 - Sharad Sinha
Low-Power FPGA Design Using Memoization-Based Approximate Computing. 2665-2678 - Himanshu Markandeya, Kaushik Roy:
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals. 2679-2688 - Yang Xiao, Siddharth Advani
A Saliency-Driven LCD Power Management System. 2689-2702 - Myat Thu Linn Aung, Eric Teck Heng Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim:
2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration. 2703-2711 - Chang-Chih Chen, Taizhi Liu, Linda Milor
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection. 2712-2725 - Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume:
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories. 2726-2734 - Daniele Rossi
Reliable Power Gating With NBTI Aging Benefits. 2735-2744 - Amit Kumar Singh, Muhammad Shafique
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors. 2745-2758 - Irith Pomeranz:
A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis. 2759-2767 - Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. 2768-2777 - Boris Vaisband, Eby G. Friedman:
Noise Coupling Models in Heterogeneous 3-D ICs. 2778-2786 - Alp Arslan Bayrakci
Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling. 2787-2798 - Hyeon Uk Sim, Atul Rahman, Jongeun Lee:
Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces. 2799-2802 - Paramjeet Singh Sahni, Suresh Chandra Joshi, Nitin Gupta, Gangaikondan Subramani Visweswaran:
An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI. 2803-2807 - Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek
A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs. 2808-2812
Volume 24, Number 9, September 2016
- Bo Yuan, Bin Li, Huanhuan Chen, Xin Yao
Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm. 2813-2826 - Chaudhry Adnan Aslam, Yong Liang Guan
Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information. 2827-2836 - Xian Li, Karthi Duraisamy, Paul Bogdan, Turbo Majumder, Partha Pratim Pande:
Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control. 2837-2850 - Sara Choi, Taehui Na
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. 2851-2860 - Kejie Huang
Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration. 2861-2872 - Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula:
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. 2873-2886 - Vishal Khatri, Gaurab Banerjee:
A 0.25-3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection. 2887-2898 - Andrew P. Nicholson, Artemij Iberzanov, Julian Jenkins, Tara Julia Hamilton
A Statistical Design Approach for a Digitally Programmable Mismatch-Tolerant High-Speed Nauta Structure Differential OTA in 65-nm CMOS. 2899-2910 - Ayman H. Ismail
A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time Σ-Δ ADC. 2911-2917 - Shyam Kumar Devarakond, Shreyas Sen, Aritra Banerjee
Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits. 2918-2931 - Esther P. Adeva, Gerhard P. Fettweis:
Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration. 2932-2945 - Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. 2946-2959 - Erhan Ozalevli
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators. 2960-2969 - Jorge Zarate-Roldan, Mengde Wang, Joselyn Torres, Edgar Sánchez-Sinencio:
A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads. 2970-2982 - Yuh-Shyan Hwang, Jiann-Jong Chen
A 10-μ s Transient Recovery Time Low-EMI DC-DC Buck Converter With Δ - Δ Modulator. 2983-2992 - Taehui Na
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM. 2993-2997 - Da-Wei Chang, Wei-Cheng Lin, Hsin-Hung Chen:
FastRead: Improving Read Performance for Multilevel-Cell Flash Memory. 2998-3002 - Mario Garrido
Multiplierless Unity-Gain SDF FFTs. 3003-3007 - Zhuo Qian, Martin Margala
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. 3008-3012
Volume 24, Number 10, October 2016
- Xianmin Chen, Niraj K. Jha:
Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network. 3013-3026 - Lei Yang, Weichen Liu
Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization. 3027-3040 - Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. 3041-3054 - Andreas Riefert, Riccardo Cantoro
A Flexible Framework for the Automatic Generation of SBST Programs. 3055-3066 - Nan Wang, Wei Zhong, Cong Hao, Song Chen
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design. 3067-3079 - Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Design Methodology for Voltage-Scaled Clock Distribution Networks. 3080-3093 - Xianzhang Chen
Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory. 3094-3104 - Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Dimitrios Soudris
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation. 3105-3117 - Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung:
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime. 3118-3131 - Ming-Chang Yang, Yuan-Hao Chang
Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices. 3132-3144 - Debao Wei, Liyan Qiao, Shiyuan Wang, Xiyuan Peng:
Fixation Ratio of Error Location-Aware Strategy for Increased Reliable Retention Time of Flash Memory. 3145-3155 - Tsung-Hsueh Lee, Pamela Abshire
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators. 3156-3168 - Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures. 3169-3183 - Sen Wang, Chih-Hsuan Lee, Yan-Bin Wu:
Fully Integrated 10-GHz Active Circulator and Quasi-Circulator Using Bridged-T Networks in Standard CMOS. 3184-3192
Volume 24, Number 11, November 2016
- Sanjeev Das
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems. 3193-3207 - Giovanni Causapruno, Fabrizio Riente
Reconfigurable Systolic Array: From Architecture to Physical Design for NML. 3208-3217 - Aida Todri-Sanial
A Study of 3-D Power Delivery Networks With Multiple Clock Domains. 3218-3231 - Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Hyuck-Sang Yim, Seong-Ook Jung:
All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator. 3232-3242 - Junshi Liu
EMBIRA: An Accelerator for Model-Based Iterative Reconstruction. 3243-3256 - Miroslav Knezevic
Low-Latency ECDSA Signature Verification - A Road Toward Safer Traffic. 3257-3267 - Yavar Safaei Mehrabani
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. 3268-3281 - Yousuke Miyake
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. 3282-3295 - Hamed Farbeh
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. 3296-3309 - Yuanqing Cheng
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. 3310-3322 - Chih-Feng Wu, Wei-Chang Liu, Chia-Chun Tsui, Chun-Yi Liu, Meng-Siou Sie, Shyh-Jye Jou:
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver. 3323-3333 - Yung-Hui Chung, Chia-Wei Yen, Meng-Hsuan Wu:
A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS. 3334-3344 - Pranab Roy
Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips. 3345-3358 - Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak:
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems. 3359-3372
Volume 24, Number 12, December 2016
- Zhe Wang, Xuan Wang, Jiang Xu, Haoran Li, Rafael K. V. Maeda, Zhehui Wang
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. 3373-3386 - Fahimeh Jafari
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip. 3387-3400 - Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan
Emulation-Based Analysis of System-on-Chip Performance Under Variations. 3401-3414 - Jun Wang
Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint. 3415-3423 - Xiaolu Wang, Huaxi Gu
A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom. 3424-3436 - Wei-Hen Lo
Architecture of Ring-Based Redundant TSV for Clustered Faults. 3437-3449 - Robert Polster
Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes. 3450-3459 - Pai-Yu Chen, Zhiwei Li
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. 3460-3467 - Ayan Paul
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. 3468-3476 - Jin-Wei Jhang, Yuan-Hao Huang
A High-SNR Projection-Based Atom Selection OMP Processor for Compressive Sensing. 3477-3488 - Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. 3489-3498 - Chenrong Xiong
A Multimode Area-Efficient SCL Polar Decoder. 3499-3512 - Yongsheng Xu
5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications. 3513-3525 - Robert Karam
Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels. 3526-3537 - Alfonso Sánchez-Macián
Optimizing the Implementation of SEC-DAEC Codes in FPGAs. 3538-3542 - Chundong Wu, Wang Ling Goh, Chiang Liang Kok
Asymmetrical Dead-Time Control Driver for Buck Regulator. 3543-3547 - Sebastian Höppner
A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring. 3548-3552
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