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Jihyuck Jo
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2020 – today
- 2023
- [c1]Seah Kim
, Hyoukjun Kwon
DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads. ASPLOS (4) 2023: 73-86 - 2022
- [i1]Seah Kim, Hyoukjun Kwon, Jinook Song, Jihyuck Jo, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra:
SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads. CoRR abs/2212.03414 (2022) - 2021
- [j8]Suchang Kim
Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2017-2029 (2021)
2010 – 2019
- 2018
- [j7]Jihyuck Jo
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. IEEE J. Solid State Circuits 53(2): 605-618 (2018) - [j6]Jihyuck Jo
Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4196-4207 (2018) - 2017
- [j5]Jihyuck Jo, In-Cheol Park
Low-Latency Low-Cost Architecture for Square and Cube Roots. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(9): 1951-1955 (2017) - 2016
- [j4]Jihyuck Jo
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 754-758 (2016) - 2014
- [j3]Byeong Yong Kong
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1648-1652 (2014) - 2013
- [j2]Youngjoo Lee
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48(10): 2531-2540 (2013) - [j1]Hoyoung Yoo
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 872-876 (2013)
Coauthor Index
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