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IEEE Journal of Solid-State Circuits, Volume 48
Volume 48, Number 1, January 2013
- Maurits Ortmanns, Timothy C. Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai:
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. 3-7 - Sven Lütkemeier, Thorsten Jungeblut
, Hans Kristian Otnes Berge, Snorre Aunet, Mario Porrmann
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. 8-19 - David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre
SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. 20-32 - Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo:
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams. 33-45 - Kenichi Okada
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. 46-65 - Matthew Fojtik, David Fick, Yejoong Kim
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. 66-81 - Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister:
The Next Generation 64b SPARC Core in a T4 SoC Processor. 82-90 - Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. 91-103 - David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. 104-117 - Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. 118-127 - Farhana Sheikh
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. 128-139 - Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger:
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. 140-149 - Eric Karl, Yih Wang
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. 150-158 - Kazushige Kanda, Noboru Shibata, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Naoki Kobayashi, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, Yasuhiko Honda, Yosuke Kato, Shingo Zaitsu, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita:
A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface. 159-167 - Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi:
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. 168-177 - Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono:
An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput. 178-185 - Alan Chi Wai Wong, Mark Dawkins, Gabriele Devita, Nick Kasparidis, Andreas G. Katsiamis, Oliver King, Franco Lauria, Johannes Schiff, Alison J. Burdett:
A 1 V 5 mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN Transceiver for Biotelemetry Applications. 186-198 - Yanqing Zhang, Fan Zhang, Yousef Shakhsheer, Jason Silver, Alicia Klinefelter, Manohar Nagaraju, James Boley, Jagdish Nayayan Pandey, Aatmesh Shrivastava, Eric J. Carlson, Austin Wood, Benton H. Calhoun, Brian P. Otis:
A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications. 199-213 - Jerald Yoo
An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor. 214-228 - Yoonmyung Lee
A Modular 1 mm3 Die-Stacked Sensing Platform With Low Power I2C Inter-Die Communication and Multi-Modal Energy Harvesting. 229-243 - Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana Jr., Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev
A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer. 244-254 - Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. 255-264 - Pedram Lajevardi, Vladimir P. Petkov, Boris Murmann
A ΔΣ Interface for MEMS Accelerometers Using Electrostatic Spring Constant Modulation for Cancellation of Bondwire Capacitance Drift. 265-275 - Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter. 276-291 - Kamran Souri, Youngcheol Chae, Kofi A. A. Makinwa:
A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of ±0.15°C (3σ) From -55°C to 125°C. 292-301 - Simone Gambini, Karl Skucha, Paul Peng Liu, Jungkyu Kim, Reut Krigel:
A 10 kPixel CMOS Hall Sensor Array With Baseline Suppression and Parallel Readout for Immunoassays. 302-317 - Yusuke Oike, Abbas El Gamal:
CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing. 318-328 - Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda
A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous. 329-338
Volume 48, Number 2, February 2013
- Un-Ku Moon:
New Associate Editor. 343 - Meisam Honarvar Nazari, Azita Emami-Neyestanak
A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication. 344-357 - Wei Cheng, Mark S. Oude Alink
A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. 358-368 - Yan Li, Zhipeng Li, Oguzhan Uyar, Yehuda Avniel, Alexandre Megretski, Vladimir Stojanovic:
High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers. 369-380 - Peter Ossieur, Nasir Abdul Quadir
A 10 Gb/s Linear Burst-Mode Receiver in 0.25 µm SiGe: C BiCMOS. 381-390 - Shih-Yuan Kao, Shen-Iuan Liu:
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection. 391-404 - Pin-Hao Feng, Shen-Iuan Liu:
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS. 405-416 - Yi-Chieh Huang, Shen-Iuan Liu:
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing. 417-428 - Wei Deng, Kenichi Okada
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. 429-440 - Liming Xiu, Win-Ting Lin, Tsung-Ta Lee:
Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC. 441-455 - In Young Choi, Heesong Seo, Bumman Kim:
Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation. 456-464 - Jinho Noh, Dongjun Lee, Jun-Gi Jo, Changsik Yoo:
A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid. 465-472 - Philip M. Chopp, Anas A. Hamoui:
A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz. 473-486 - Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez:
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. 487-501 - Omid Rajaee, Un-Ku Moon:
Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End. 502-515 - Jun-Seok Kim, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS. 516-526 - Zushu Yan, Pui-In Mak
A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW. 527-540 - Hyunsik Kim
An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution. 541-558 - Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato, Manabu Kagami:
A 100-m Range 10-Frame/s 340,x,96-Pixel Time-of-Flight Depth Sensor in 0.18-µm CMOS. 559-572 - Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. 573-586 - Ioannis Savidis, Selçuk Köse
Power Noise in TSV-Based 3-D Integrated Circuits. 587-597 - Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim:
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. 598-610 - Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement. 611-623
Volume 48, Number 3, March 2013
- Un-Ku Moon:
New Associate Editor. 635 - Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan:
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver. 636-648 - Kshitij Yadav, Ioannis Kymissis, Peter R. Kinget:
A 4.4-µW Wake-Up Receiver Using Ultrasound Data. 649-660 - Jonathan K. Brown, David D. Wentzloff:
A GSM-Based Clock-Harvesting Receiver With -87 dBm Sensitivity for Sensor Network Wake-Up. 661-669 - Bing-Nan Fang, Jieh-Tsorng Wu:
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation. 670-683 - Jun Won Jung, Behzad Razavi:
A 25-Gb/s 5-mW CMOS CDR/Deserializer. 684-697 - Chih-Wei Yao, Alan N. Willson Jr.:
A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO. 698-710 - Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim:
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. 711-723 - Andrea Mazzanti, Pietro Andreani:
A Push-Pull Class-C CMOS VCO. 724-732 - Seyed Danesh, Jed Hurwitz, Keith Findlater, David R. Renshaw, Robert K. Henderson:
A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design. 733-748 - Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling. 749-759 - Tae-Hwang Kong, Young-Jin Woo, Se-Won Wang, Yong-Joon Jeon, Sung-Wan Hong, Gyu-Hyeong Cho:
Zeroth-Order Control of Boost DC-DC Converter With Transient Enhancement Scheme. 760-773 - Deepak Bhatia, Lin Xue, Pengfei Li, Qiuzhong Wu, Rizwan Bashirullah:
High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process. 774-789 - Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. 790-800 - Matthew Fojtik, Daeyeon Kim, Gregory K. Chen, Yu-Shiang Lin, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, David T. Blaauw, Dennis Sylvester:
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells. 801-813 - Simeon Realov, Kenneth L. Shepard:
On-Chip Combined C-V/I-V Characterization System in 45-nm CMOS Technology. 814-826 - Teresa Serrano-Gotarredona
A 128×128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers. 827-838 - Shang-Fu Yeh, Chih-Cheng Hsieh, Ka-Yi Yeh:
A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers. 839-849 - Nicola Cottini, Massimo Gottardi, Nicola Massari
A 33 µW 64×64 Pixel Vision Sensor Embedding Robust Dynamic Background Subtraction for Event Detection and Scene Interpretation. 850-863 - Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. 864-877 - Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. 878-891
Volume 48, Number 4, April 2013
- Vivek De, Hideyuki Kabuo:
Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits. 895-896 - Tsung-Te Liu, Jan M. Rabaey:
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression. 897-906 - Keith A. Bowman
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. 907-916 - Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki:
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. 917-923 - Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara:
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. 924-931 - Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort:
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation. 932-939 - Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. 940-947 - Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. 948-959 - William Biederman, Daniel J. Yeager, Nathan Narevsky, Aaron C. Koralek
A Fully-Integrated, Miniaturized (0.125 mm2) 10.5 µW Wireless Neural Sensor. 960-970 - Dusan Stepanovic, Borivoje Nikolic
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS. 971-982 - Gerry Taylor, Ian Galton:
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB. 983-995 - Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. 996-1008 - KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. 1009-1017 - Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. 1018-1030 - Po-Shuan Weng, Hao-Yen Tang, Po-Chih Ku, Liang-Hung Lu:
50 mV-Input Batteryless Boost Converter for Thermal Energy Harvesting. 1031-1041 - Arun Paidimarri
A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier. 1042-1054 - Amin Arbabian, Steven Callender, Shinwon Kang, Mustafa Rangwala, Ali M. Niknejad:
A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition. 1055-1071 - Joung Won Park, Behzad Razavi:
A Harmonic-Rejecting CMOS LNA for Broadband Radios. 1072-1084 - Tamer A. Ali, Robert J. Drost, Ron Ho, Chih-Kong Ken Yang:
A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. 1085-1098 - Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam:
Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers. 1099-1108
Volume 48, Number 5, May 2013
- Shahriar Shahramian, Yves Baeyens, Noriaki Kaneda, Young-Kai Chen:
A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link. 1113-1125 - Andreea Balteanu, Ioannis Sarkas, Eric Dacquay, Alexander Tomkins, Gabriel M. Rebeiz, Peter M. Asbeck, Sorin P. Voinigescu:
A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters. 1126-1137 - Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. 1138-1150 - Seungkee Min, Tino Copani, Sayfe Kiaei, Bertan Bakkaloglu
A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation. 1151-1160 - Tzung-Han Wu, Hsiang-Hui Chang, Shin-Fu Chen, Chinq-Shiun Chiu, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Chi-Yao Yu, Sheng-Yuan Su, Tai-Yuan Yu, Chieh-Chuan Chin, Guang-Kaai Dehng, Augusto Marques, Caiyi Wang, George Chien:
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM. 1161-1173 - Tieng Yi Choke, Hongke Zhang, Sam Chun-Geik Tan, W. Yang, Ying Chow Tan, Satyanarayana Reddy Karri, Yuan Sun, Dan Ping Li, Zwei-Mei Lee, Tianbao Gao, Weimin Shu, Osama Shana'a
A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS. 1174-1187 - Caroline Andrews, Luke Diamente, Dong Yang, Ben Johnson, Alyosha C. Molnar:
A Wideband Receiver With Resonant Multi-Phase LO and Current Reuse Harmonic Rejection Baseband. 1188-1198 - Bodhisatwa Sadhu
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. 1199-1211 - Sang-Min Yoo, Jeffrey S. Walling
A Class-G Switched-Capacitor RF Power Amplifier. 1212-1224 - Venumadhav Bhagavatula, William Wesson, Soon-Kyun Shin, Jacques Christophe Rudell:
A Fully Integrated, Regulatorless CMOS Power Amplifier for Long-Range Wireless Sensor Communication. 1225-1236 - Xin Wang, Zitao Shi, Jian Liu, Lin Lin, Hui Zhao, Li Wang, Rui Ma, Chen Zhang, Zongyu Dong, Siqiang Fan, He Tang, Albert Z. Wang, Yuhua Cheng, Bin Zhao, Zhigang Zhang, Baoyong Chi, Tianling Ren:
Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis. 1237-1249 - Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. 1250-1263 - Cheng Li, Samuel Palermo:
A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier. 1264-1275 - Young-Hoon Song, Rui Bai, Kangmin Hu, Noah Hae-Woong Yang, Patrick Yin Chiang, Samuel Palermo:
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS. 1276-1289 - Drew A. Hall
A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS. 1290-1301 - Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. 1302-1314 - Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. 1315-1322
Volume 48, Number 6, June 2013
- Kyujin Oh, Swaminathan Sankaran, Hsin-Ta Wu, Jau-Jr Lin, Minsoon Hwang, Kenneth K. O:
Full-Duplex Crystalless CMOS Transceiver With an On-Chip Antenna for Wireless Communication in a Hybrid Engine Controller Board. 1327-1342 - Amir Ghaffari, Eric A. M. Klumperink, Bram Nauta
Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification. 1370-1382 - Taehyoun Oh, Ramesh Harjani:
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS. 1383-1397 - Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. 1416-1428 - Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. 1429-1441 - Bibhudatta Sahoo, Behzad Razavi:
A 10-b 1-GHz 33-mW CMOS ADC. 1442-1452 - Marcus Yip, Anantha P. Chandrakasan:
A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications. 1453-1464 - Chih-Wen Lu, Ching-Min Hsiao, Ping-Yeh Yin:
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs. 1475-1486 - Ben Johnson, Alyosha C. Molnar:
An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing. 1487-1496 - Hadar Dagan, Adam Teman
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. 1497-1510 - Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. 1530-1538 - Zushu Yan, Pui-In Mak
Correction to "A 0.016 mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW". 1539 - Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa:
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". 1540 - Aravind Heragu, David Ruffieux, Christian C. Enz:
A Low Power BAW Resonator Based 2.4-GHz Receiver With Bandwidth Tunable Channel Selection Filter at RF. 1343-1356 - Shervin Moloudi, Asad A. Abidi:
The Outphasing RF Power Amplifier: A Comprehensive Analysis and a Class-B CMOS Realization. 1357-1369 - Hyung-Joon Jeon, Raghavendra Kulkarni, Yung-Chung Lo, Jusung Kim, José Silva-Martínez:
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. 1398-1415 - Taehwan Oh, Nima Maghari, Un-Ku Moon:
A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer. 1465-1474 - Takashi Ohsawa
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. 1511-1520 - Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms. 1521-1529 - Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". 1539
Volume 48, Number 7, July 2013
- Antonio Liscidini
Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC). 1555-1557 - Hans Meyvaert, Patrick Smeets, Michiel Steyaert
A 265 VRMS Mains Interface Integrated in 0.35 µm CMOS. 1558-1564 - Jens Masuch, Manuel Delgado-Restituto
Co-Integration of an RF Energy Harvester Into a 2.4 GHz Transceiver. 1565-1574 - Jiawei Xu, Qinwen Fan, Johan H. Huijsing, Chris Van Hoof
Measurement and Analysis of Current Noise in Chopper Amplifiers. 1575-1584 - Richard Jan Engel Jansen, Johan Haanstra, David Sillars Greenpeak:
Complementary Constant-gm Biasing of Nauta-Transconductors in Low-Power gm-C Filters to ±2% Accuracy Over Temperature. 1585-1594 - Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult:
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. 1595-1604 - Thomas Christen:
A 15-bit 140-µW Scalable-Bandwidth Inverter-Based ΔΣ Modulator for a MEMS Microphone With Digital Output. 1605-1614 - Gyeonghoon Kim, Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo:
An 86 mW 98GOPS ANN-Searching Processor for Full-HD 30 fps Video Object Recognition With Zeroless Locality-Sensitive Hashing. 1615-1624 - Kyong-Ho Lee, Naveen Verma:
A Low-Power Processor With Configurable Embedded Machine-Learning Accelerators for High-Order and Adaptive Analysis of Medical-Sensor Signals. 1625-1637 - Edward M. D. Fisher
A Reconfigurable Single-Photon-Counting Integrating Receiver for Optical Communications. 1638-1650 - Gerben W. de Jong, Domine Leenaerts, Edwin van der Heijden:
A Fully Integrated Ka-Band VSAT Down-Converter. 1651-1658 - Lars Sundström
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. 1659-1668 - Jorge Carballido, Jorge Hermosillo, Arturo Veloz-Guerrero, David Arditti, Alberto Del Rio, Edgar Borrayo Sandoval, Manuel E. Guzman-Renteria, Hasnain Lakdawala, Marian Verhelst
A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver. 1669-1679 - Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
An 0.8-mm2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS. 1680-1688 - Aravind Heragu, David Ruffieux, Christian C. Enz:
A 2.4-GHz MEMS-Based PLL-Free Multi-Channel Receiver With Channel Filtering at RF. 1689-1700 - Shiyuan Zheng, Howard C. Luong
A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization. 1701-1709 - Wei Deng, Teerachot Siriburanon
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. 1710-1720 - Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi:
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. 1721-1729 - Luca Fanori, Pietro Andreani:
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs. 1730-1740 - Matteo Bassi
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer. 1741-1750 - Janus Grzyb, Yan Zhao, Ullrich R. Pfeiffer
A 288-GHz Lens-Integrated Balanced Triple-Push Source in a 65-nm CMOS Technology. 1751-1761
Volume 48, Number 8, August 2013
- Un-Ku Moon:
Message From the Outgoing Editor-in-Chief. 1767 - Michael P. Flynn:
Message From the Incoming Editor-in-Chief. 1768 - Ken Suyama, Hasnain Lakdawala:
Introduction to the Special Issue on the IEEE 2012 Custom Integrated Circuits Conference. 1769-1770 - Pio Balmelli, John M. Khoury, Eduardo Viegas, Paulo Santos, Vitor Pereira, Jeffrey Alderson, Richard Beale:
A Low-EMI 3-W Audio Class-D Amplifier Compatible With AM/FM Radio. 1771-1782 - Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. 1783-1794 - Timir Nandi, Karthikeya Boominathan, Shanthi Pavan:
Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC. 1795-1805 - Behzad Razavi:
Design Considerations for Interleaved ADCs. 1806-1817 - Jiangfeng Wu, Chun-Ying Chen, Tianwei Li, Lin He, Wenbo Liu, Wei-Ta Shih, Shauhyuarn Sean Tsai, Binning Chen, Chun-Sheng Huang, Bryan Juo-Jung Hung, Hing T. Hung, Steven Jaffe, Loke Kun Tan, Hung Vu:
A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization. 1818-1828 - Amer Samarah, Anthony Chan Carusone
A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC. 1829-1841 - Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto:
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation. 1842-1850 - Jun Yin
A 57.5-90.1-GHz Magnetically Tuned Multimode CMOS VCO. 1851-1861 - Aslam A. Rafi, T. R. Viswanathan:
Harmonic Rejection Mixing Techniques Using Clock-Gating. 1862-1874 - Namik Kocaman, Siavash Fallahi, Mahyar Kargar, Mehdi Khanpour, Ali Nazemi, Ullas Singh, Afshin Momtaz:
An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition. 1875-1884 - Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, Samuel Palermo:
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS. 1885-1897 - Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon:
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters. 1898-1909 - Sudhir S. Kudva, Ramesh Harjani:
Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. 1910-1920 - Massimo Alioto, Elio Consoli, Jan M. Rabaey:
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions. 1921-1932 - Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. 1933-1942 - Eustace Painkras, Luis A. Plana
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. 1943-1953 - Min Huang, Moty Mehalel, Ramesh Arvapalli, Songnian He:
An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family. 1954-1962 - Arijit Raychowdhury, Carlos Tokunaga
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. 1963-1969 - Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim:
A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing. 1970-1985 - Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. 1986-1994
Volume 48, Number 9, September 2013
- Michael P. Flynn:
New Associate Editor. 1999 - Fa Foster Dai:
Introduction to the Special Section on the 26th Bipolar/BiCMOS Circuits and Technology Meeting. 2000-2001 - Richard Al Hadi, Janus Grzyb, Bernd Heinemann, Ullrich R. Pfeiffer
A Terahertz Detector Array in a SiGe HBT Technology. 2002-2010 - Sorin P. Voinigescu, Alexander Tomkins, Eric Dacquay, Pascal Chevalier
A Study of SiGe HBT Signal Sources in the 220-330-GHz Range. 2011-2021 - Gang Liu, Hermann Schumacher:
Broadband Millimeter-Wave LNAs (47-77 GHz and 70-140 GHz) Using a T-Type Matching Topology. 2022-2029 - Ruili Wu, Yen-Ting Liu, Jerry Lopez, Cliff Schecht, Yan Li, Donald Y. C. Lie:
High-Efficiency Silicon-Based Envelope-Tracking Power Amplifier Design With Envelope Shaping for Broadband Wireless Applications. 2030-2040 - Woorim Shin, Bon-Hyun Ku, Ozgur Inac, Yu-Chin Ou, Gabriel M. Rebeiz:
A 108-114 GHz 4 × 4 Wafer-Scale Phased Array Transmitter With High-Efficiency On-Chip Antennas. 2041-2055 - Mehmet Uzunkol, Ozan D. Gurbuz, Fatih Golcuk, Gabriel M. Rebeiz:
A 0.32 THz SiGe 4x4 Imaging Array Using High-Efficiency On-Chip Antennas. 2056-2066 - Mohyee Mikhemar, Hooman Darabi, Asad A. Abidi:
A Multiband RF Antenna Duplexer on CMOS: Design and Performance. 2067-2077 - Ka-Fai Un
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS. 2078-2089 - Jusung Kim, José Silva-Martínez:
Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications. 2090-2103 - Mohamed M. Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio:
A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS. 2104-2117 - Seon-Kyoo Lee
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. 2118-2127 - Peter A. Davies:
A 3.3/2.5 V-Supply 2400 mV-Swing Single-Ended SiGe BiCMOS Driver With Programmable Preemphasis for 3 Gb/s Data Transmission Over 75 Ω Coaxial Cable. 2128-2141 - Dingkun Du, Kofi M. Odame:
A Bandwidth-Adaptive Preamplifier. 2142-2153 - Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. 2154-2169 - Su-Hao Wu, Jieh-Tsorng Wu:
A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. 2170-2179 - Colin Weltin-Wu, Yannis P. Tsividis:
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution. 2180-2190 - Matthias Kuhl, Pascal Gieschke, Daniel Rossbach, Sascha Alexander Hilzensauer, Thanapon Panchaphongsaphak, Patrick Ruther, Bernd G. Lapatki, Oliver Paul, Yiannos Manoli:
A Wireless Stress Mapping System for Orthodontic Brackets Using CMOS Integrated Sensors. 2191-2202 - Hyung-Min Lee
A Power-Efficient Wireless System With Adaptive Supply Control for Deep Brain Stimulation. 2203-2216 - Louis H. Jung, Nitzan Shany, Alexander Emperle, Torsten Lehmann, Phil Byrnes-Preston, Nigel H. Lovell, Gregg J. Suaning
Design of Safe Two-Wire Interface-Driven Chip-Scale Neurostimulator for Visual Prosthesis. 2217-2229 - Vaibhav Karkare, Sarah Gibson, Dejan Markovic:
A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering. 2230-2238 - Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. 2239-2249 - Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Sue-Meng Yang, Ku-Feng Lin, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih:
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. 2250-2259
Volume 48, Number 10, October 2013
- Hossein Hashemi:
Introduction to the 34th Annual IEEE Compound Semiconductor Integrated Circuit Symposium. 2263-2264 - Bert K. Oyama, Daniel Ching, Khanh Thai, Augusto Gutierrez-Aitken, Vipul J. Patel
InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR. 2265-2272 - Minoru Fujishima
98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits. 2273-2284 - Gijs van der Bent, Peter de Hek, Sander Geurts, Ali Telli, Herve Brouzes, Michiel Besselink, Frank E. van Vliet:
A 10 Watt S-Band MMIC Power Amplifier With Integrated 100 MHz Switch-Mode Power Supply and Control Circuitry for Active Electronically Scanned Arrays. 2285-2295 - Ruonan Han, Yaming Zhang, Youngwan Kim, Dae Yeon Kim, Hisashi Shichijo, Ehsan Afshari, Kenneth K. O:
Active Terahertz Imaging Using Schottky Diodes in CMOS: Array and 860-GHz Pixel. 2296-2308 - Liang Wu, Alvin Li, Howard C. Luong
A 4-Path 42.8-to-49.5 GHz LO Generation With Automatic Phase Tuning for 60 GHz Phased-Array Receivers. 2309-2322 - Dixian Zhao, Patrick Reynaert
A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS. 2323-2337 - Amir Agah, Hayg-Taniel Dabag, Bassel Hanafi, Peter M. Asbeck, James F. Buckwalter, Lawrence E. Larson:
Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS. 2338-2350 - Dominique Morche, Gilles Masson, Sébastien de Rivaz, Francois Dehmas
Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision. 2351-2362 - Travis Forbes
Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency. 2363-2374 - Federico Pepe
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. 2375-2389 - Wei Cheng, Anne-Johan Annema
A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. 2390-2402 - Yue Chao, Howard C. Luong
Analysis and Design of a 2.9-mW 53.4-79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS. 2403-2418 - Salvatore Levantino
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. 2419-2429 - Hao Luo, Yan Han, Ray C. C. Cheung
A 0.8-V 230-µW 98-dB DR Inverter-Based ΣΔ Modulator for Audio Applications. 2430-2441 - Xiaocheng Jing, Philip K. T. Mok
A Fast Fixed-Frequency Adaptive-On-Time Boost Converter With Light Load Efficiency Enhancement and Predictable Noise Spectrum. 2442-2456 - Sung-Wan Hong, Tae-Hwang Kong, Sang-Hui Park, Changbyung Park, Seungchul Jung, Sungwoo Lee, Gyu-Hyeong Cho:
High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC). 2457-2468 - Zhichao Tan, Roel Daamen, Aurelie Humbert, Youri Ponomarev, Youngcheol Chae, Michiel A. P. Pertijs:
A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications. 2469-2477 - Karim Abdelhalim, Larysa Kokarovtseva, José Luis Pérez Velazquez, Roman Genov:
915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters. 2478-2493 - Karim Abdelhalim, Hamed Mazhab-Jafari, Larysa Kokarovtseva, José Luis Pérez Velazquez, Roman Genov:
64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator. 2494-2510 - Yoonmyung Lee
A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes. 2511-2521 - Meng-Ting Chung, Chin-Lin Lee, Chin Yin, Chih-Cheng Hsieh:
A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise. 2522-2530 - Youngjoo Lee
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. 2531-2540 - Henry Park, Chih-Kong Ken Yang:
In Situ SRAM Static Stability Estimation in 65-nm CMOS. 2541-2549 - Daeyong Shim, Hyunsik Jeong, Hyunjoong Lee, Cyuyeol Rhee
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. 2550-2557 - Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. 2558-2569
Volume 48, Number 11, November 2013
- Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. 2582-2594 - Cheng Huang
An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency. 2595-2607 - Kazuhiro Ueda, Fukashi Morishita
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. 2608-2617 - Jelle Van Rethy, Hans Danneels, Valentijn De Smedt
Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS. 2618-2627 - Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. 2628-2636 - Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Yu-Hsin Lin:
A 64-fJ/Conv.-Step Continuous-Time Sigma Delta Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Delta Sigma Truncator. 2637-2648 - Shen-Yu Peng, Tzu-Chi Huang, Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings. 2649-2661 - Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. 2662-2670 - Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. 2671-2680 - Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang:
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. 2681-2692 - Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung-Hoon Kim, E-Hung Chen, Brian S. Leibowitz, Jaeha Kim:
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm. 2693-2704 - Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Fule Li, Weitao Li, Jia Gao, Jianwei Cui, Baoyong Chi, Chun Zhang, Zhihua Wang:
A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO. 2705-2716 - Yuan Gao
An Asymmetrical QPSK/OOK Transceiver SoC and 15: 1 JPEG Encoder IC for Multifunction Wireless Capsule Endoscopy. 2717-2733 - Kailiang Chen, Hae-Seung Lee, Anantha P. Chandrakasan, Charles G. Sodini:
Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver. 2734-2745 - Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Samuel Er-Shen Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. 2746-2761 - Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Minghua Tang, Zhao-Wen Zhuang:
A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications. 2762-2774 - Jing-Hwa Chen, S. R. Helmi, R. Azadegan, Farshid Aryanfar, S. Mohammadi:
A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology. 2775-2784 - Wanghua Wu, John R. Long, Robert Bogdan Staszewski
High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators. 2785-2794 - Dong-Woo Jee, Yunjae Suh, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL. 2795-2804 - Yingchieh Ho, Yu-Sheng Yang, Chiachi Chang, Chauchin Su:
A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO. 2805-2814 - Shih-Yuan Kao, Shen-Iuan Liu:
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection. 2815-2826 - Ming-Feng Huang, Ming-Ching Kuo, Tzu-Yi Yang, Xuan-Lun Huang:
A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS. 2827-2838 - Orlando Lazaro, Gabriel A. Rincón-Mora:
180-nm CMOS Wideband Capacitor-Free Inductively Coupled Power Receiver and Charger. 2839-2849 - Erdogan Ozgur Ates, Atilim Ergul, Devrim Yilmaz Aksin
Fully Integrated Frequency Reference With 1.7 ppm Temperature Accuracy Within 0-80°C. 2850-2859 - Joseph S. Shor, Kosta Luria:
Miniaturized BJT-Based Thermal Sensor for Microprocessors in 32- and 22-nm Technologies. 2860-2867 - Mohammad Reza Nabavi, Michiel A. P. Pertijs, Stoyan N. Nihtianov:
An Interface for Eddy-Current Displacement Sensors With 15-bit Resolution and 20 MHz Excitation. 2868-2881 - Rami A. Abdallah, Naresh R. Shanbhag:
An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation. 2882-2893 - Jinwook Oh, Gyeonghoon Kim, Byeong-Gyu Nam
A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition. 2894-2907 - Rahul Rithe, Priyanka Raina
Reconfigurable Processor for Energy-Efficient Computational Photography. 2908-2919 - Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). 2920-2933 - Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. 2934-2943 - Chang-Hyun Kim, Hong June Park, Woogeun Rhee
Introduction to the Special Section on the 2012 Asian Solid-State Circuits Conference (A-SSCC). 2579-2581
Volume 48, Number 12, December 2013
- Marco Berkhout, Lutsen Dooper, Benno Krabbenborg:
A 4Ω 2.65W Class-D Audio Amplifier With Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for Adaptive Speaker Protection. 2952-2961 - Milad Darvishi, Ronan A. R. van der Zee
Design of Active N-Path Filters. 2962-2976 - Cheng Huang
A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction. 2977-2988 - Jun-Han Choi, Sung-Ku Yeo, Seho Park, Jeong-Seok Lee, Gyu-Hyeong Cho:
Resonant Regulating Rectifiers (3R) Operating for 6.78 MHz Resonant Wireless Power Transfer (RWPT). 2989-3001 - Stefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof
A High Voltage Self-Biased Integrated DC-DC Buck Converter With Fully Analog MPPT Algorithm for Electrostatic Energy Harvesters. 3002-3010 - Pieter Harpe, Eugenio Cantatore, Arthur H. M. van Roermund:
A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step. 3011-3018 - Youngcheol Chae, Kamran Souri, Kofi A. A. Makinwa:
A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset. 3019-3027 - Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee:
A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability. 3028-3037 - Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos:
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. 3038-3048 - Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. 3049-3058 - Ron Kapusta
A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS. 3059-3066 - Ivan Fabiano, Marco Sosio, Antonio Liscidini
SAW-Less Analog Front-End Receivers for TDD and FDD. 3067-3079 - Mohyee Mikhemar, David Murphy, Ahmad Mirzaei, Hooman Darabi:
A Cancellation Technique for Reciprocal-Mixing Caused by Phase Noise and Spurs. 3080-3089 - Ruonan Han, Ehsan Afshari:
A CMOS High-Power Broadband 260-GHz Radiator Array for Spectroscopy. 3090-3104 - Luca Fanori, Pietro Andreani:
Class-D CMOS Oscillators. 3105-3119 - Masoud Babaie, Robert Bogdan Staszewski
A Class-F CMOS Oscillator. 3120-3133 - Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. 3134-3145 - Noriaki Saito, Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka
A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage. 3146-3159 - Lu Ye, Jiashu Chen, Lingkai Kong, Elad Alon, Ali M. Niknejad:
Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation. 3160-3177 - Kuo-Ken Huang, Jonathan K. Brown, Elnaz Ansari, Ryan R. Rogel, Yoonmyung Lee
An Ultra-Low-Power 9.8 GHz Crystal-Less UWB Transceiver With Digital Baseband Integrated in 0.18 µm BiCMOS. 3178-3189 - Fan Zhang, Yasunori Miyahara, Brian P. Otis:
Design of a 300-mV 2.4-GHz Receiver Using Transformer-Coupled Techniques. 3190-3205 - John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray:
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. 3206-3218 - Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao:
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. 3219-3228 - Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. 3229-3242 - Yue Lu, Elad Alon:
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS. 3243-3257 - Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. 3258-3267 - Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. 3268-3284 - Clifford Ting, Joshua Liang
A Blind Baud-Rate ADC-Based CDR. 3285-3295 - Piero Malcovati
Introduction to the Special Issue on the 2013 IEEE International Solid-State Circuits Conference. 2947-2951
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