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Alberto Valdes-Garcia
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2020 – today
- 2024
- [j28]Arun Paidimarri
, Asaf Tzadok, Sara Garcia Sanchez
Eye-Beam: A mmWave 5G-Compliant Platform for Integrated Communications and Sensing Enabling AI-Based Object Recognition. IEEE J. Sel. Areas Commun. 42(9): 2354-2368 (2024) - [j27]Wooram Lee
A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency. IEEE J. Solid State Circuits 59(9): 2788-2804 (2024) - 2023
- [j26]Tingjun Chen
Open-access millimeter-wave software-defined radios in the PAWR COSMOS testbed: Design, deployment, and experimentation. Comput. Networks 234: 109922 (2023) - [c24]Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman:
Cryogenic CMOS: design considerations for future quantum computing systems. CICC 2023: 1-8 - 2022
- [j25]Bodhisatwa Sadhu
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. IEEE J. Solid State Circuits 57(12): 3599-3616 (2022) - [c23]Tim Lee, Harish Krishnaswamy, Paolo Gargini, Earl McCune, Harrison Chang, Anding Zhu, Alberto Valdes-Garcia:
INGR Millimeter Wave and Signal Processing Roadmap - 2022 Edition. FNWF 2022: 1354-1413 - [c22]Bodhisatwa Sadhu, Arun Paidimarri
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. ISSCC 2022: 436-438 - 2020
- [j24]Wooram Lee
Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS. IEEE J. Solid State Circuits 55(5): 1187-1198 (2020) - [j23]Bodhisatwa Sadhu
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55(6): 1516-1529 (2020)
2010 – 2019
- 2018
- [j22]Wooram Lee
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C. IEEE J. Solid State Circuits 53(9): 2512-2531 (2018) - [c21]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman:
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS 2018: 80-84 - [c20]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Yahya M. Tousi, Duixian Liu, Scott K. Reynolds, Joakim Hallin, Stefan Sahl, Leonard Rexberg:
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules. CICC 2018: 1-8 - [c19]Bodhisatwa Sadhu, Arun Paidimarri
A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation. mmNets 2018: 21-25 - [c18]Xiaoxiong Gu, Bodhisatwa Sadhu, Duixian Liu, Christian W. Baks, Alberto Valdes-Garcia:
Antenna-in-package design and module integration for millimeter-wave communication and 5G. VLSI-DAT 2018: 1-2 - 2017
- [j21]Bodhisatwa Sadhu
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. IEEE J. Solid State Circuits 52(12): 3373-3391 (2017) - [c17]Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia:
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. ISSCC 2017: 128-129 - 2015
- [j20]Xiaoxiong Gu
W-band scalable phased arrays for imaging and communications. IEEE Commun. Mag. 53(4): 196-204 (2015) - [j19]Bodhisatwa Sadhu
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. IEEE J. Solid State Circuits 50(5): 1214-1223 (2015) - [c16]Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia:
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information. ICCAD 2015: 575-582 - 2014
- [j18]Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test 31(6): 8-18 (2014) - [j17]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - 2013
- [j16]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48(4): 996-1008 (2013) - [j15]Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j14]Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j13]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [c15]Mihai A. T. Sanduleanu
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. CICC 2013: 1-4 - [c14]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - [c13]Wayne H. Woods, Alberto Valdes-Garcia, Hanyi Ding, Jay Rascoe:
CMOS millimeter wave phase shifter based on tunable transmission lines. CICC 2013: 1-4 - 2012
- [j12]Haralampos-G. D. Stratigopoulos, Alberto Valdes-Garcia:
Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers. IEEE Des. Test Comput. 29(6): 5-6 (2012) - [c12]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c11]Alberto Valdes-Garcia:
Silicon-based THz circuits, systems and applications (Forum). CICC 2012: 1 - [c10]Alberto Valdes-Garcia, Ramesh Harjani:
Radio receiver techniques. CICC 2012: 1 - [c9]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177 - 2011
- [j11]Alberto Valdes-Garcia, Scott K. Reynolds, Arun Natarajan, Dong Gun Kam, Duixian Liu, Jie-Wei Lai, Yen-Lin Oscar Huang, Ping-Yu Chen, Ming-Da Tsai, Jing-Hong Conan Zhan, Sean Nicolson, Brian A. Floyd
Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications. IEEE Commun. Mag. 49(4): 120-131 (2011) - [j10]Arun Natarajan
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 46(5): 1059-1075 (2011) - 2010
- [j9]Alberto Valdes-Garcia, Sean T. Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Brian A. Floyd
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications. IEEE J. Solid State Circuits 45(12): 2757-2773 (2010) - [c8]Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications. ISSCC 2010: 218-219 - [c7]Jie-Wei Lai, Alberto Valdes-Garcia:
A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS. ISSCC 2010: 424-425
2000 – 2009
- 2009
- [j8]Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez:
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1467-1477 (2009) - 2008
- [j7]Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio:
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements. IEEE Trans. Instrum. Meas. 57(7): 1470-1477 (2008) - [c6]Yasunao Katayama, Daiju Nakano, Alberto Valdes-Garcia, Troy J. Beukema, Scott K. Reynolds:
Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections. ICME 2008: 513-516 - 2007
- [j6]Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio:
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. IEEE J. Solid State Circuits 42(4): 935-948 (2007) - [c5]Alberto Valdes-Garcia, Scott K. Reynolds, Troy J. Beukema:
Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers. CICC 2007: 639-642 - 2006
- [j5]Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio:
On-Chip Testing Techniques for RF Wireless Transceivers. IEEE Des. Test Comput. 23(4): 268-277 (2006) - [j4]Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver. IEEE J. Solid State Circuits 41(3): 530-539 (2006) - [j3]Alberto Valdes-Garcia, Faisal Abdel-Latif Hussien, José Silva-Martínez, Edgar Sánchez-Sinencio:
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing. IEEE J. Solid State Circuits 41(10): 2301-2313 (2006) - [j2]Ahmed A. Emira, Alberto Valdes-Garcia, Bo Xia, A. N. Mohieldin
Chameleon: a dual-mode 802.11b/Bluetooth receiver system design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 992-1003 (2006) - 2005
- [j1]Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio:
An On-Chip Spectrum Analyzer for Analog Built-In Testing. J. Electron. Test. 21(3): 205-219 (2005) - [c4]Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio:
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. VTS 2005: 249-254 - 2004
- [c3]Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
A configurable time-interleaved pipeline ADC for multi-standard wireless receivers. ESSCIRC 2004: 259-262 - [c2]Ari Yakov Valero-López, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
Frequency synthesizer for on-chip testing and automated tuning. ISCAS (4) 2004: 565-568 - [c1]Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio:
An On-Chip Transfer Function Characterization System for Analog Built-in Testing. VTS 2004: 261-266
Coauthor Index
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