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Soner Yaldiz
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2020 – today
- 2024
- [j10]Arvind K. Sharma
, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee
Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4373-4385 (2024) - 2023
- [j9]Ramprasath Srinivasa Gopalakrishnan
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - [c16]Soner Yaldiz
Analog Layout Automation On Advanced Process Technologies. ISPD 2023: 103 - 2022
- [c15]Tonmoy Dhar, Ramprasath S
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE 2022: 148-153 - [c14]Ramprasath S
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166 - 2021
- [j8]Tonmoy Dhar, Kishor Kunal
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [c13]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE 2021: 1224-1229 - [c12]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD 2021: 1-9 - [c11]Tonmoy Dhar, Kishor Kunal
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - 2020
- [c10]Tonmoy Dhar, Kishor Kunal
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [i1]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020)
2010 – 2019
- 2015
- [c9]Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd:
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. CICC 2015: 1-4 - 2014
- [j7]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - 2013
- [j6]Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry T. Pileggi:
Formal verification of phase-locked loops using reachability analysis and continuization. Commun. ACM 56(10): 97-104 (2013) - [j5]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48(4): 996-1008 (2013) - [j4]Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j3]Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j2]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [c8]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - 2012
- [c7]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c6]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177 - 2011
- [c5]Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno:
Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC 2011: 1-4 - [c4]Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi:
Formal verification of phase-locked loops using reachability analysis and continuization. ICCAD 2011: 659-666
2000 – 2009
- 2009
- [c3]Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi:
SRAM parametric failure analysis. DAC 2009: 496-501 - [c2]Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi:
Efficient statistical analysis of read timing failures in SRAM circuits. ISQED 2009: 617-621 - 2008
- [j1]Soner Yaldiz, Alper Demir
Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1264-1277 (2008) - 2005
- [c1]Soner Yaldiz, Alper Demir
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTIMedia 2005: 135-140
Coauthor Index
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